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公开(公告)号：US20050262416A1
公开(公告)日：2005-11-24
申请号：US11133430
申请日：2005-05-20
CPC分类号： G11B20/1833 , G11B20/1866 , G11B2020/184
摘要： To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to its writing in a memory (101), data from a host is input to an EDC arithmetic operation circuit (110) and a scrambling arithmetic operation circuit (111) to be processed, and then the error correction codes are added to the data written in the memory (101) from the scrambling arithmetic operation circuit (111) by a PI arithmetic operation circuit (104) and a PO arithmetic operation circuit (105). Accordingly, it is possible to omit memory access when the data is written from the host in the memory, and memory access when the data is read from the memory to the EDC arithmetic operation circuit. Thus, it is possible to reduce an operation clock frequency of the memory (101).
摘要翻译： 为了提供一种即使在低操作时钟频率的存储器中也可以通过减少访问存储器的次数来确保记录操作的实时性的同时降低功耗和存储器成本的数据编码电路。 在写入存储器（101）之前，将来自主机的数据输入到EDC算术运算电路（110）和加扰算术运算电路（111）进行处理，然后将纠错码加到数据 通过PI运算电路（104）和PO算术运算电路（105）从加扰运算电路（111）写入存储器（101）。 因此，当数据从存储器中的主机写入时，可以省略存储器访问，以及当数据从存储器读取到EDC算术运算电路时的存储器访问。 因此，可以减小存储器（101）的操作时钟频率。
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公开(公告)号：US4901318A
公开(公告)日：1990-02-13
申请号：US184335
申请日：1988-04-21
申请人： Shin'ichiro Tomisawa
发明人： Shin'ichiro Tomisawa
CPC分类号： G11B20/10527 , G11B20/1809 , G11B27/3063 , G11B2220/213 , G11B2220/2545
摘要： An address generating circuit (13) generates a reading address for reading a buffer memory (16) so that so-called P and Q codes for a CD-ROM which have parameters i and j can be decoded. The reading address is obtainable based on a formula RDA=H+2L+p, where H is a starting address of one block not inluding synchronous signal or pattern, L is a symbolic location of a symbol, and p is a sign for designating that the symbol is included in a LSB byte plane or an MSB byte plane. A first full adder (25) generates the symbolic location L based on the parameter i and j with various constants being given from a constant generator (23) so as to give the symbolic location L to a second full adder (21). The starting address H is given from a writing address pointer (12a). The second full adder adds H, 2L and p to apply the reading address to an address bus. In addition, the symbolic location L is latched in a symbol off-set address (26) and, if necessary, fed-back to the first full adder through multiplexers (24, 27) when the next symbolic location is to be generated.
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3.发明授权Audio data recording/reproducing apparatus having digital high-speed dubbing function 失效具有数字高速复录功能的音频数据记录/重放装置
公开(公告)号：US5363364A
公开(公告)日：1994-11-08
申请号：US876365
申请日：1992-04-30
IPC分类号： G11B20/02 , G11B11/105 , G11B20/10 , G11B27/00 , G11B27/034 , G11B27/10 , G11B5/02 , G11B27/02
CPC分类号： G11B27/034 , G11B11/10502 , G11B20/10527 , G11B27/10 , G11B2220/20 , G11B2220/213 , G11B2220/2525 , G11B2220/2545 , G11B27/002
摘要： A disc recording/reproducing apparatus according to the present invention intermittently records and reproduces compressed digital audio data in normal recording/reproduction. In high-speed dubbing of digital audio data, two of such apparatuses are used, wherein compressed digital audio data is continuously reproduced from a disc for reproduction by the reproduction side apparatus to be directly applied to the recording side apparatus and continuously recorded on a disc for recording. Thus, the compressed high-speed dubbing of the digital audio data can be achieved without increasing a rotation speed of the disc even in high-speed dubbing.
摘要翻译： 根据本发明的盘记录/再现装置在正常记录/再现中间歇地记录和再现压缩的数字音频数据。 在数字音频数据的高速转录中，使用了两个这样的装置，其中压缩的数字音频数据从盘再连续再现，以便由再现侧装置再现以直接应用到记录侧装置并连续记录在盘上 用于录音。 因此，即使在高速配音中也可以不增加盘的旋转速度来实现数字音频数据的压缩高速转录。
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公开(公告)号：US20050262417A1
公开(公告)日：2005-11-24
申请号：US11133459
申请日：2005-05-20
CPC分类号： G11B20/1866 , G11B20/1833 , G11B2020/184
摘要： To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to its writing in a memory (101), data from a host is processed by an EDC arithmetic operation circuit (110) and a scrambling arithmetic operation circuit (111), and written in the memory (101). Next, error correction encoding of a PO direction is executed at a PO arithmetic operation circuit (105), and an obtained PO code is added to corresponding data to be written in the memory (101). Subsequently, the data are read in a PI direction line by line from the memory (101) to a PI arithmetic operation circuit (112). A PI code is added to the data, and the data are sequentially output to a modulation circuit (200). Thus, it is possible to omit memory access when the data is written from the host in the memory, memory access when the data is read from the memory to the EDC arithmetic operation circuit, memory access when the data is read from the memory (101) to the modulation circuit (200), and memory access when the error correction code is written from the PI arithmetic operation circuit in the memory. As a result, it is possible to greatly reduce an operation clock frequency of the memory.
摘要翻译： 为了提供一种即使在低操作时钟频率的存储器中也可以通过减少访问存储器的次数来确保记录操作的实时性的同时降低功耗和存储器成本的数据编码电路。 在写入存储器（101）之前，来自主机的数据由EDC算术运算电路（110）和加扰算术运算电路（111）处理，并写入存储器（101）。 接下来，在PO算术运算电路（105）中执行PO方向的纠错编码，并且将获得的PO码添加到要写入存储器（101）的相应数据。 随后，从存储器（101）到PI运算电路（112）逐行读取PI方向的数据。 将PI代码添加到数据中，并且数据被顺序地输出到调制电路（200）。 因此，当从存储器中的主机写入数据时，可以省略存储器访问，当从存储器读取数据到EDC算术运算电路时的存储器访问，当从存储器读取数据时的存储器存取 ）到调制电路（200），以及当从存储器中的PI运算电路写入纠错码时的存储器访问。 结果，可以大大降低存储器的操作时钟频率。
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公开(公告)号：US20050283512A1
公开(公告)日：2005-12-22
申请号：US11133457
申请日：2005-05-20
CPC分类号： G11B20/1833
摘要： To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to error correction encoding of a PI direction, error correction encoding of a PO direction is carried out at a PO arithmetic operation circuit (105), and an obtained PO code is added to corresponding data and written in a memory (101). Subsequently, data are read line by line in a PI direction from the memory (101) to a PI arithmetic operation circuit (110), a PI code is added to the data, and the data are sequentially output to a modulation circuit (200). Thus, it is possible to omit memory access when the data is read from the memory (101) to the modulation circuit (200) and memory access when the error correction code is written in the memory by the PI arithmetic operation circuit. As a result, it is possible to reduce an operation clock frequency of the memory.
摘要翻译： 为了提供一种即使在低操作时钟频率的存储器中也可以通过减少访问存储器的次数来确保记录操作的实时性的同时降低功耗和存储器成本的数据编码电路。 在PI方向的纠错编码之前，在PO算术运算电路（105）上进行PO方向的纠错编码，并将获得的PO码加到对应的数据上，并写入存储器（101）。 随后，从存储器（101）到PI运算电路（110）的PI方向逐行读取数据，将PI代码附加到数据，并且数据被顺序地输出到调制电路（200） 。 因此，当通过PI算术运算电路将误差校正码写入存储器时，当从存储器（101）向调制电路（200）读取数据和存储器访问时，可以省略存储器存取。 结果，可以减少存储器的操作时钟频率。
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