利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.011 秒)

    Multi-chip package semiconductor device
    1.
    发明授权
    Multi-chip package semiconductor device 有权
    多芯片封装半导体器件

    公开(公告)号：US07893757B2

    公开(公告)日：2011-02-22

    申请号：US11945030

    申请日：2007-11-26

    申请人： Tomofumi Watanabe ,  Satoshi Noro ,  Satoshi Yokoo

    发明人： Tomofumi Watanabe ,  Satoshi Noro ,  Satoshi Yokoo

    IPC分类号： H01L25/00

    CPC分类号： H04N5/23248 ,  H01L25/18 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H04N5/23287 ,  H01L2924/00

    摘要： An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chip power supply circuit is provided in which a driver chip creates a logic chip power supply dedicated for the logic chip. The logic chip has internal logic circuitry operating by receiving a power supply from the logic chip power supply circuit via power input terminals.

    摘要翻译： 提供了具有多芯片封装中的数字电路的高效逻辑芯片工作电源。 与具有模拟电路的驱动器芯片和具有数字电路的逻辑芯片共同制造的多芯片封装半导体器件，提供了一种逻辑芯片电源电路，其中驱动器芯片产生专用于逻辑芯片的逻辑芯片电源。 逻辑芯片具有通过从逻辑芯片电源电路经由电源输入端子接收电源来工作的内部逻辑电路。

    Circuit and method for encoding data and data recorder
    3.
    发明申请
    Circuit and method for encoding data and data recorder 审中-公开
    用于编码数据和数据记录器的电路和方法

    公开(公告)号：US20050283512A1

    公开(公告)日：2005-12-22

    申请号：US11133457

    申请日：2005-05-20

    申请人： Miyuki Okamoto ,  Masato Fuma ,  Shin'ichiro Tomisawa ,  Satoshi Noro ,  Hidemitsu Senoo

    发明人： Miyuki Okamoto ,  Masato Fuma ,  Shin'ichiro Tomisawa ,  Satoshi Noro ,  Hidemitsu Senoo

    IPC分类号： G11B20/10 ,  G06F11/08 ,  G06F17/14 ,  G11B20/12 ,  G11B20/18

    CPC分类号： G11B20/1833

    摘要： To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to error correction encoding of a PI direction, error correction encoding of a PO direction is carried out at a PO arithmetic operation circuit (105), and an obtained PO code is added to corresponding data and written in a memory (101). Subsequently, data are read line by line in a PI direction from the memory (101) to a PI arithmetic operation circuit (110), a PI code is added to the data, and the data are sequentially output to a modulation circuit (200). Thus, it is possible to omit memory access when the data is read from the memory (101) to the modulation circuit (200) and memory access when the error correction code is written in the memory by the PI arithmetic operation circuit. As a result, it is possible to reduce an operation clock frequency of the memory.

    摘要翻译： 为了提供一种即使在低操作时钟频率的存储器中也可以通过减少访问存储器的次数来确保记录操作的实时性的同时降低功耗和存储器成本的数据编码电路。 在PI方向的纠错编码之前，在PO算术运算电路（105）上进行PO方向的纠错编码，并将获得的PO码加到对应的数据上，并写入存储器（101）。 随后，从存储器（101）到PI运算电路（110）的PI方向逐行读取数据，将PI代码附加到数据，并且数据被顺序地输出到调制电路（200） 。 因此，当通过PI算术运算电路将误差校正码写入存储器时，当从存储器（101）向调制电路（200）读取数据和存储器访问时，可以省略存储器存取。 结果，可以减少存储器的操作时钟频率。

    MULTI-CHIP PACKAGE SEMICONDUCTOR DEVICE
    5.
    发明申请
    MULTI-CHIP PACKAGE SEMICONDUCTOR DEVICE 有权
    多芯片封装半导体器件

    公开(公告)号：US20090128229A1

    公开(公告)日：2009-05-21

    申请号：US11945030

    申请日：2007-11-26

    申请人： Tomofumi Watanabe ,  Satoshi Noro ,  Satoshi Yokoo

    发明人： Tomofumi Watanabe ,  Satoshi Noro ,  Satoshi Yokoo

    IPC分类号： H03K3/38

    CPC分类号： H04N5/23248 ,  H01L25/18 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H04N5/23287 ,  H01L2924/00

    摘要： An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chip power supply circuit is provided in which a driver chip creates a logic chip power supply dedicated for the logic chip. The logic chip has internal logic circuitry operating by receiving a power supply from the logic chip power supply circuit via power input terminals.

    摘要翻译： 提供了一种具有多芯片封装中的数字电路的高效逻辑芯片工作电源。 与具有模拟电路的驱动器芯片和具有数字电路的逻辑芯片共同制造的多芯片封装半导体器件，提供了一种逻辑芯片电源电路，其中驱动器芯片产生专用于逻辑芯片的逻辑芯片电源。 逻辑芯片具有通过从逻辑芯片电源电路经由电源输入端子接收电源来工作的内部逻辑电路。

    Decoder
    8.
    发明授权
    Decoder 有权
    解码器

    公开(公告)号：US07209641B2

    公开(公告)日：2007-04-24

    申请号：US10444100

    申请日：2003-05-22

    申请人： Satoshi Noro

    发明人： Satoshi Noro

    IPC分类号： H04N7/087

    CPC分类号： G11B20/10009 ,  G11B20/1403 ,  H04N5/85

    摘要： A decoder having improved accuracy for reading data. The decoder decodes reproduced data including preamble data, to which a first synchronization pattern is added, and information data, which follows the preamble data and to which a second synchronization pattern is added. The decoder includes a memory for storing a first, second, and third comparison patterns respectively corresponding to the first synchronization pattern, the preamble data, and the second synchronization pattern. A comparison circuit compares the first synchronization pattern, the preamble data, and the second synchronization pattern respectively with the corresponding comparison patterns. A determination circuit generates a start signal to start decoding when at least two of the first synchronization pattern, the preamble data, and the second synchronization pattern match the corresponding comparison pattern. A decoding circuit starts error correction of the reproduced data in response to the start signal.

    摘要翻译： 一种具有读取数据的精度提高的解码器。 解码器解码再现数据，包括添加有第一同步模式的前导码数据和跟随前导码数据并添加了第二同步模式的信息数据。 解码器包括用于存储分别对应于第一同步模式，前导码数据和第二同步模式的第一，第二和第三比较模式的存储器。 比较电路将第一同步模式，前导码数据和第二同步模式分别与对应的比较模式进行比较。 当第一同步模式，前导码数据和第二同步模式中的至少两个与对应的比较模式匹配时，确定电路产生开始解码的开始信号。 解码电路响应于起始信号开始再现数据的纠错。

    Access circuit with various access data units
    9.
    发明授权
    Access circuit with various access data units 有权
    具有各种接入数据单元的接入电路

    公开(公告)号：US07111122B2

    公开(公告)日：2006-09-19

    申请号：US10649366

    申请日：2003-08-27

    申请人： Satoshi Noro ,  Shin-ichiro Tomisawa

    发明人： Satoshi Noro ,  Shin-ichiro Tomisawa

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1006 ,  G11C11/4082 ,  G11C11/4096

    摘要： An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of the access circuit may be switched between one byte, one word, and two words. The switching of the access data unit is performed in accordance with a data unit designation signal generated by decoding address data, which is provided to a control unit, with an address decoder. The memory interface receives a request signal that is in accordance with the data unit designation signal from a request generator and accesses the buffer memory in the access data unit that is in accordance with the request signal.

    摘要翻译： 一种用于根据来自外部电路的指令高效地访问缓冲存储器的访问电路。 用于在访问电路的一个操作时钟周期中访问SDRAM的访问数据单元可以在一个字节，一个字和两个字之间切换。 访问数据单元的切换根据通过解码提供给控制单元的地址数据而产生的数据单元指定信号与地址解码器来执行。 存储器接口接收来自请求发生器的与数据单元指定信号相对应的请求信号，并访问与请求信号相对应的访问数据单元中的缓冲存储器。

    Decoder
    10.
    发明授权
    Decoder 有权
    解码器

    公开(公告)号：US07035182B2

    公开(公告)日：2006-04-25

    申请号：US10770778

    申请日：2004-02-03

    申请人： Satoshi Noro ,  Shin-ichiro Tomisawa

    发明人： Satoshi Noro ,  Shin-ichiro Tomisawa

    IPC分类号： G11B20/10

    CPC分类号： G11B27/24 ,  G11B7/0053 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2562

    摘要： A decoder for improving the reliability of synchronization pattern detection. The decoder includes a synchronization circuit for detecting a synchronization pattern from LPP data and wobble data. A first frame counter is reset when a synchronization detection circuit detects the synchronization pattern of a first sector and counts the number of frames of data until the synchronization pattern of the next sector is detected. A comparison circuit compares a count value of the first frame counter with a first reference value, which corresponds to the number of frames for one sector. A determination circuit determines whether or not the detected synchronization pattern is proper based on the comparison result of the comparison circuit.

    摘要翻译： 一种用于提高同步模式检测可靠性的解码器。 解码器包括用于从LPP数据和摆动数据检测同步模式的同步电路。 当同步检测电路检测到第一扇区的同步模式时，第一帧计数器被复位，并对数据帧数进行计数，直到检测到下一个扇区的同步模式。 比较电路将第一帧计数器的计数值与对应于一个扇区的帧数的第一参考值进行比较。 确定电路基于比较电路的比较结果来确定检测到的同步模式是否正确。