公开(公告)号：US20080211544A1

公开(公告)日：2008-09-04

申请号：US12000304

申请日：2007-12-11

申请人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： H03K5/1532

CPC分类号： G01R19/04

摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

公开(公告)号：US08008948B2

公开(公告)日：2011-08-30

申请号：US12000304

申请日：2007-12-11

申请人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： G01R19/00 ,  G06M1/10

CPC分类号： G01R19/04

摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

摘要翻译： 峰值电压检测电路检测输入电压的峰值电压。 输入电压被输入到比较器的第一输入端。 当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。 计数器电路与第二个时钟信号同步地计数计数器值。 数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。 第一时钟信号具有比第二时钟信号短的波周期。

公开(公告)号：US20090002033A1

公开(公告)日：2009-01-01

申请号：US12213893

申请日：2008-06-26

申请人： Shinji Nakatani ,  Nobukazu Oba ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Shinji Nakatani ,  Nobukazu Oba ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： H03K5/22

CPC分类号： H03K5/1252 ,  H03K5/086

摘要： The present invention reliably removes a signal change associated with a noise component from a comparison signal of a comparator. A comparator circuit includes a comparator and a timer circuit. After a reversal of the comparison signal, if the level of the comparator is sustained at least from a first time to a second time, an output signal is reversed and output. The timer circuit includes a memory unit that is shifted to a memory state in which the reversal of the comparison signal is stored at the first time if the reversal is verified. If the comparison signal is reversed during the interval between the first time and second time, the memory state is cleared.

摘要翻译： 本发明可以从比较器的比较信号可靠地去除与噪声分量相关联的信号变化。 比较器电路包括比较器和定时器电路。 在比较信号反转之后，如果比较器的电平至少从第一时间持续到第二时间，则输出信号被反转并输出。 定时器电路包括一个存储器单元，该存储器单元被转移到如果反转被验证则在第一时间存储比较信号的反转的存储器状态。 如果在第一次和第二次之间的间隔期间比较信号反转，则存储器状态被清除。

公开(公告)号：US20070285291A1

公开(公告)日：2007-12-13

申请号：US11717169

申请日：2007-03-13

申请人： Yasuaki Makino ,  Susumu Kuroyanagi ,  Shinji Nakatani ,  Reiji Iwamoto ,  Hideki Hosokawa ,  Norikazu Ohta

发明人： Yasuaki Makino ,  Susumu Kuroyanagi ,  Shinji Nakatani ,  Reiji Iwamoto ,  Hideki Hosokawa ,  Norikazu Ohta

IPC分类号： H03M1/12

CPC分类号： H03K5/003 ,  H03K3/3565 ,  H03K5/084 ,  H04L25/063

摘要： A binarization circuit for binarizing a pulsative analog signal includes: a first comparator circuit for reversing an output signal when the analog signal becomes smaller than a threshold voltage and when the analog signal becomes larger than a high side threshold voltage; a second comparator circuit for reversing an output signal when the analog signal becomes larger than the threshold voltage and when the analog signal becomes smaller than a low side threshold voltage; and a selector circuit for inputting the output signals from the first and second comparator circuits and for reversing an output signal when the analog signal becomes smaller than the threshold voltage and when the analog signal becomes larger than the threshold voltage.

摘要翻译： 用于二值化脉冲模拟信号的二值化电路包括：第一比较器电路，用于当模拟信号变得小于阈值电压时以及当模拟信号变得大于高侧阈值电压时反转输出信号; 第二比较器电路，用于当模拟信号变得大于阈值电压时以及当模拟信号变得小于低侧阈值电压时反转输出信号; 以及选择器电路，用于输入来自第一和第二比较器电路的输出信号，并且当模拟信号变得小于阈值电压时以及当模拟信号变得大于阈值电压时反转输出信号。

公开(公告)号：US06452381B1

公开(公告)日：2002-09-17

申请号：US09198567

申请日：1998-11-23

申请人： Shinji Nakatani ,  Hirofumi Uenoyama ,  Takamasa Kinpara

发明人： Shinji Nakatani ,  Hirofumi Uenoyama ,  Takamasa Kinpara

IPC分类号： G01B730

CPC分类号： G01D5/147

摘要： In a position detecting device for a moving object, such as a camshaft gear, having ridges and valleys, magnetoresistive elements are disposed in positions offset in the rotation direction of the moving object from the magnetic center of a bias magnetic field projected by a bias magnet. The direction of the bias magnetic field is different when the moving object is in a ridge position from when it is in a valley position. A mid-point potential of the MREs is taken as the output of an MRE bridge to obtain an output value which is different when the moving object is in the ridge position from when it is in the valley position. It is thus possible to distinguish between the ridge position and the valley position of the moving object.

摘要翻译： 在具有脊和谷的诸如凸轮轴齿轮的运动物体的位置检测装置中，磁阻元件设置在从由偏置磁体投射的偏置磁场的磁心的移动物体的旋转方向上偏移的位置 。 当移动物体处于从山谷位置处的脊位置时，偏置磁场的方向是不同的。 将MRE的中点电位作为MRE桥的输出，以获得当移动物体处于山谷位置时处于脊位置时不同的输出值。 因此可以区分移动物体的脊位置和谷位置。

公开(公告)号：US6130619A

公开(公告)日：2000-10-10

申请号：US978518

申请日：1992-11-20

申请人： Shinji Nakatani

发明人： Shinji Nakatani

IPC分类号： G06F11/30 ,  G06F13/00 ,  H04L1/24 ,  H04L29/14 ,  G05B23/02

CPC分类号： H04L1/246

摘要： A watch-dog type monitoring circuit for a communication device has a counter and a timer. The communication device outputs a communication signal including plural groups of pulse-string signals. The maximum number of pulses in each group of pulse-string signals and the minimum idle time between successive groups of pulse-string signals are previously prescribed by a communications protocol. The counter counts pulses and outputs an abnormal condition signal when a counted number exceeds a predetermined number. The timer inputs the communication signal, measures the idle time between successive groups of pulse-string signals, and resets the counter when the measured idle time exceeds a predetermined amount of time. Since the monitoring circuit monitors whether the communication device is in an abnormal condition by judging the normality of the communication signal, it an abnormal condition of not only the communication device to which the monitoring device is connected but also an abnormal condition of earlier-stages of the communication system.

摘要翻译： 用于通信设备的看门狗型监视电路具有计数器和定时器。 通信装置输出包括多组脉冲串信号的通信信号。 每组脉冲串信号中的最大脉冲数和连续的脉冲串信号组之间的最小空闲时间预先由通信协议规定。 计数器计数脉冲，并且当计数数超过预定数量时输出异常状态信号。 定时器输入通信信号，测量连续的脉冲串信号组之间的空闲时间，并在测量的空闲时间超过预定时间量时重置计数器。 由于监视电路通过判断通信信号的正常状态来监视通信装置是否处于异常状态，不仅是监视装置所连接的通信装置的异常状况，而且还包括早期阶段的异常状况 通信系统。