公开(公告)号：US20080211544A1

公开(公告)日：2008-09-04

申请号：US12000304

申请日：2007-12-11

申请人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： H03K5/1532

CPC分类号： G01R19/04

摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

公开(公告)号：US20070285291A1

公开(公告)日：2007-12-13

申请号：US11717169

申请日：2007-03-13

申请人： Yasuaki Makino ,  Susumu Kuroyanagi ,  Shinji Nakatani ,  Reiji Iwamoto ,  Hideki Hosokawa ,  Norikazu Ohta

发明人： Yasuaki Makino ,  Susumu Kuroyanagi ,  Shinji Nakatani ,  Reiji Iwamoto ,  Hideki Hosokawa ,  Norikazu Ohta

IPC分类号： H03M1/12

CPC分类号： H03K5/003 ,  H03K3/3565 ,  H03K5/084 ,  H04L25/063

摘要： A binarization circuit for binarizing a pulsative analog signal includes: a first comparator circuit for reversing an output signal when the analog signal becomes smaller than a threshold voltage and when the analog signal becomes larger than a high side threshold voltage; a second comparator circuit for reversing an output signal when the analog signal becomes larger than the threshold voltage and when the analog signal becomes smaller than a low side threshold voltage; and a selector circuit for inputting the output signals from the first and second comparator circuits and for reversing an output signal when the analog signal becomes smaller than the threshold voltage and when the analog signal becomes larger than the threshold voltage.

摘要翻译： 用于二值化脉冲模拟信号的二值化电路包括：第一比较器电路，用于当模拟信号变得小于阈值电压时以及当模拟信号变得大于高侧阈值电压时反转输出信号; 第二比较器电路，用于当模拟信号变得大于阈值电压时以及当模拟信号变得小于低侧阈值电压时反转输出信号; 以及选择器电路，用于输入来自第一和第二比较器电路的输出信号，并且当模拟信号变得小于阈值电压时以及当模拟信号变得大于阈值电压时反转输出信号。

公开(公告)号：US06960485B2

公开(公告)日：2005-11-01

申请号：US10375135

申请日：2003-02-28

申请人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

发明人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

IPC分类号： H01L33/00 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01L33/60 ,  H01L21/00

CPC分类号： H01L33/46 ,  H01L33/0095 ,  H01L33/32

摘要： A process of forming separation grooves for separating a semiconductor wafer into individual light-emitting devices, a process for thinning the substrate, process for adhering the wafer to the adhesive sheet to expose a substrate surface on the reverse or backside of the wafer, a scribing process for forming split lines in the substrate for dividing the wafer into light-emitting devices, and a process of forming a mirror structure comprising a light transmission layer, a reflective layer, and a corrosion-resistant layer, which are laminated in sequence using sputtering or deposition processes. Because the light transmission layer is laminated on the adhesive sheet, gases normally volatilized from the adhesion materials are sealed and do not chemically combine with the metal being deposited as the reflective layer. As a result, reflectivity of the reflective layer can be maintained.

摘要翻译： 形成用于将半导体晶片分离成各个发光器件的分离槽的工艺，用于使基板变薄的工艺，将晶片粘附到粘合片上以暴露晶片背面或背面的基板表面的处理，划线 在基板上形成分割线以将晶片分割成发光器件的工艺，以及形成包括透光层，反射层和耐腐蚀层的反射镜结构的工艺，其顺序地使用溅射 或沉积工艺。 由于透光层层压在粘合片上，所以通常从粘合材料挥发的气体被密封，并且不与作为反射层沉积的金属化学结合。 结果，可以保持反射层的反射率。

公开(公告)号：US20050133799A1

公开(公告)日：2005-06-23

申请号：US11034261

申请日：2005-01-13

申请人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

发明人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

IPC分类号： H01L33/00 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01L33/60 ,  H01L21/00 ,  H01L27/10 ,  H01L27/15 ,  H01L29/26 ,  H01L29/74 ,  H01L31/12

CPC分类号： H01L33/46 ,  H01L33/0095 ,  H01L33/32

摘要： A process of forming separation grooves for separating a semiconductor wafer into individual light-emitting devices, a process for thinning the substrate, process for adhering the wafer to the adhesive sheet to expose a substrate surface on the reverse or backside of the wafer, a scribing process for forming split lines in the substrate for dividing the wafer into light-emitting devices, and a process of forming a mirror structure comprising a light transmission layer, a reflective layer, and a corrosion-resistant layer, which are laminated in sequence using sputtering or deposition processes. Because the light transmission layer is laminated on the adhesive sheet, gases normally volatilized from the adhesion materials are sealed and do not chemically combine with the metal being deposited as the reflective layer. As a result, reflectivity of the reflective layer can be maintained.

公开(公告)号：US08008948B2

公开(公告)日：2011-08-30

申请号：US12000304

申请日：2007-12-11

申请人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Nobukazu Oba ,  Shinji Nakatani ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： G01R19/00 ,  G06M1/10

CPC分类号： G01R19/04

摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

摘要翻译： 峰值电压检测电路检测输入电压的峰值电压。 输入电压被输入到比较器的第一输入端。 当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。 计数器电路与第二个时钟信号同步地计数计数器值。 数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。 第一时钟信号具有比第二时钟信号短的波周期。

公开(公告)号：US20090002033A1

公开(公告)日：2009-01-01

申请号：US12213893

申请日：2008-06-26

申请人： Shinji Nakatani ,  Nobukazu Oba ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Shinji Nakatani ,  Nobukazu Oba ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： H03K5/22

CPC分类号： H03K5/1252 ,  H03K5/086

摘要： The present invention reliably removes a signal change associated with a noise component from a comparison signal of a comparator. A comparator circuit includes a comparator and a timer circuit. After a reversal of the comparison signal, if the level of the comparator is sustained at least from a first time to a second time, an output signal is reversed and output. The timer circuit includes a memory unit that is shifted to a memory state in which the reversal of the comparison signal is stored at the first time if the reversal is verified. If the comparison signal is reversed during the interval between the first time and second time, the memory state is cleared.

摘要翻译： 本发明可以从比较器的比较信号可靠地去除与噪声分量相关联的信号变化。 比较器电路包括比较器和定时器电路。 在比较信号反转之后，如果比较器的电平至少从第一时间持续到第二时间，则输出信号被反转并输出。 定时器电路包括一个存储器单元，该存储器单元被转移到如果反转被验证则在第一时间存储比较信号的反转的存储器状态。 如果在第一次和第二次之间的间隔期间比较信号反转，则存储器状态被清除。

公开(公告)号：US20080048641A1

公开(公告)日：2008-02-28

申请号：US11822291

申请日：2007-07-03

申请人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Norikazu Ohta ,  Hideki Hosokawa

发明人： Yasuaki Makino ,  Hiroshi Okada ,  Reiji Iwamoto ,  Norikazu Ohta ,  Hideki Hosokawa

IPC分类号： G01R19/04

CPC分类号： G01R19/04

摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

摘要翻译： 峰值电压检测电路检测输入电压的峰值电压。 输入电压被输入到比较器的第一输入端。 当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。 计数器电路与第二个时钟信号同步地计数计数器值。 数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。 第一时钟信号具有比第二时钟信号短的波周期。

公开(公告)号：US4809654A

公开(公告)日：1989-03-07

申请号：US103460

申请日：1987-10-01

申请人： Takayuki Ogasawara ,  Akinori Wakasa ,  Hideki Hosokawa ,  Minoru Machida ,  Itsuo Kondo

发明人： Takayuki Ogasawara ,  Akinori Wakasa ,  Hideki Hosokawa ,  Minoru Machida ,  Itsuo Kondo

IPC分类号： F02B19/16

CPC分类号： F02B19/165 ,  Y02T10/125

摘要： A ceramic precombustion chamber construction of an internal combustion engine includes at least one ceramic body having a circular cross-section, a metal ring in which the ceramic body is fixed by shrinkage fitting, and at least one key interposed between the ceramic body and the metal ring for preventing rotation therebetween. Contour lines of a key receiving notch formed in an inner circumference of the metal ring are positioned on inner sides of contour lines of a key receiving notch formed in an outer circumference of the ceramic body. With the arrangement, the ceramic body is prevented from loosening from the fitting with the metal ring due to heat and vibration in use and is prevented from being damaged resulting from cracks occurring in the ceramic body.

摘要翻译： 内燃机的陶瓷预燃室结构包括至少一个具有圆形横截面的陶瓷体，金属环，陶瓷体通过收缩固定而固定，以及至少一个插入在陶瓷体和金属之间的键 环，用于防止它们之间的旋转。 形成在金属环的内圆周上的键接收槽的轮廓线位于形成在陶瓷体的外周的键接收槽的轮廓线的内侧。 通过该布置，由于使用中的热和振动，陶瓷体被防止由于金属环的配件而松动，并且防止陶瓷体由于陶瓷体中的裂纹而被损坏。