公开(公告)号：US20090278716A1

公开(公告)日：2009-11-12

申请号：US12436289

申请日：2009-05-06

申请人： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

发明人： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

IPC分类号： H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。