公开(公告)号：US07136308B2

公开(公告)日：2006-11-14

申请号：US10979345

申请日：2004-11-01

申请人： Shree Kant ,  Kenway Tam ,  Poonacha P. Kongetira ,  Yuan-Jung D Lin ,  Zhen W. Liu ,  Kathirgamar Aingaran

发明人： Shree Kant ,  Kenway Tam ,  Poonacha P. Kongetira ,  Yuan-Jung D Lin ,  Zhen W. Liu ,  Kathirgamar Aingaran

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C7/10 ,  G11C7/24

摘要： A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

摘要翻译： 存储器系统包括有源存储电路和至少一个基本存储电路。 至少一个基本存储电路通过至少一个传递门，至少一个驱动器和位线耦合到有源存储电路。 所述至少一个传递门和所述至少一个驱动器具有与所述有源存储电路和所述至少一个基本存储电路中的每个器件的器件尺寸基本相似的器件尺寸。 还描述了在两个存储电路之间交换数据的方法。

公开(公告)号：US07203100B2

公开(公告)日：2007-04-10

申请号：US11040058

申请日：2005-01-21

申请人： Shree Kant ,  Kathirgamar Aingaran ,  Yuan-Jung D Lin ,  Kenway Tam

发明人： Shree Kant ,  Kathirgamar Aingaran ,  Yuan-Jung D Lin ,  Kenway Tam

IPC分类号： G11C7/10

CPC分类号： G06F9/3851

摘要： A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

摘要翻译： 一种包括多个条目的多线程存储器系统，所述多个条目中的每一个包括多个线程，所述多个线程中的每一个包括活动小区和共享读取小区。 共享读取单元具有耦合到读位线的输出和耦合到多个线程中的每一个中的相应活动单元的输出的相应多个输入。 还描述了一种多线程存储器系统。