公开(公告)号：US06327555B1

公开(公告)日：2001-12-04

申请号：US09300283

申请日：1999-04-27

申请人： Shunkichi Shimizu ,  Mikio Mukai ,  Yasutoshi Komatsu

发明人： Shunkichi Shimizu ,  Mikio Mukai ,  Yasutoshi Komatsu

IPC分类号： G06F1750

CPC分类号： G06F17/5018

摘要： Impurity profiles Pi1 and Ps1 are determined for the same conditions by a reference acquiring means and a simulation capable of producing a result faster than the reference acquiring means, respectively. Errors between the impurity profile Pi1 determined by the reference acquiring means and the impurity profile Ps1 determined by the simulation are determined. An impurity profile Psx is calculated for another kind of conditions by the simulation, and a new impurity profile Psx′ is calculated by correcting the impurity profile Psx so as to reflect the errors.

摘要翻译： 通过参考获取装置和能够比参考获取装置分别产生更快的结果的模拟来确定相同条件下的杂质分布Pi1和Ps1。 由参考获取装置确定的杂质分布Pi1与通过模拟确定的杂质分布Ps1之间的误差被确定。 通过模拟计算另一种条件的杂质分布Psx，通过校正杂质分布Psx来计算新的杂质分布Psx'，以反映误差。

公开(公告)号：US6084274A

公开(公告)日：2000-07-04

申请号：US936761

申请日：1997-09-24

申请人： Mikio Mukai ,  Yutaka Hayashi ,  Yasutoshi Komatsu

发明人： Mikio Mukai ,  Yutaka Hayashi ,  Yasutoshi Komatsu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/108

摘要： A semiconductor memory cell includes a read-out transistor of a first conductivity type which has source/drain regions constituted by a second conductive region and a third semiconducting region, a channel forming region constituted by a surface region of a second semiconducting region, and a conductive gate formed on a barrier layer; a switching transistor of a second conductivity type which has source/drain regions constituted by a first conductive region and the second semiconducting region, a channel forming region constituted by a surface region of a first semiconducting region, and a conductive gate formed on a barrier layer; and a current controlling junction-field-effect transistor of a first conductivity type which has gate regions constituted by a third conductive region and a portion of the second semiconducting region, a channel region constituted by a portion of the third semiconducting region, and one source/drain region extended from one end of the channel region, being constituted by a portion of the third semiconducting region, and another source/drain region extended from the other end of the channel region, being constituted by a portion of the third semiconducting region.

摘要翻译： 半导体存储单元包括第一导电类型的读出晶体管，其具有由第二导电区域和第三半导体区域构成的源极/漏极区域，由第二半导体区域的表面区域构成的沟道形成区域，以及 导电栅极形成在阻挡层上; 第二导电类型的开关晶体管，其具有由第一导电区域和第二半导体区域构成的源极/漏极区域，由第一半导体区域的表面区域构成的沟道形成区域和形成在阻挡层上的导电栅极 ; 以及第一导电类型的电流控制结场效应晶体管，其具有由第三导电区域和第二半导体区域的一部分构成的栅极区域，由第三半导体区域的一部分构成的沟道区域和一个源极 漏极区域由沟道区域的一部分延伸，由第三半导体区域的一部分构成，另一个源极/漏极区域从沟道区域的另一端延伸，由第三半导体区域的一部分构成。

公开(公告)号：US6104639A

公开(公告)日：2000-08-15

申请号：US998281

申请日：1997-12-24

申请人： Yutaka Hayashi ,  Mikio Mukai ,  Yasutoshi Komatsu

发明人： Yutaka Hayashi ,  Mikio Mukai ,  Yasutoshi Komatsu

IPC分类号： G11C11/401 ,  G11C11/402 ,  G11C11/404 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： G11C11/404 ,  H01L27/108

摘要： A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, and (E) a non-linear resistance element having at least two ends with one end connected to the first gate.

摘要翻译： 一种在其栅极上具有存储电荷的存储单元，包括（A）沟道形成区，（B）形成在形成在沟道形成区的表面上的绝缘层上的第一栅极，第一栅极和沟道形成区域面对 彼此通过绝缘层，（C）与第一栅极电容耦合的第二栅极，（D）与沟道形成区域接触形成的源极/漏极区域，一个源极/漏极区域与另一个间隔开，（E ）具有至少两端的非线性电阻元件，其一端连接到第一栅极。

公开(公告)号：US06347050B1

公开(公告)日：2002-02-12

申请号：US09538369

申请日：2000-03-29

申请人： Mikio Mukai ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Yutaka Hayashi

IPC分类号： G11C1604

CPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/405

摘要： A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

摘要翻译： 一种半导体存储单元，包括：（1）第一导电类型的第一晶体管，用于读出，具有由第三区域和第二区域的表面区域构成的源极/漏极区域;以及沟道形成区域， （2）具有由第一区域和第四区域构成的源极/漏极区域的第二导电类型的第二导电类型的第二晶体管和由第三区域的表面区域构成的沟道形成区域，以及（3） ）具有第一导电类型的用于电流控制的结场效应晶体管，其具有由第四区域和与第四区域相对的第一区域的一部分组成的栅极区域，由第四区域夹持的第三区域和 第一区域和源极/漏极区域由第三区域组成。

公开(公告)号：US5376559A

公开(公告)日：1994-12-27

申请号：US172731

申请日：1993-12-27

申请人： Mikio Mukai ,  Masahiko Einaga ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Masahiko Einaga ,  Yutaka Hayashi

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66772 ,  H01L29/78648 ,  H01L29/78654 ,  Y10S148/012 ,  Y10S438/928

摘要： A lateral insulating gate type field effect transistor can be manufactured with ease reliably by using a semiconductor substrate having excellent crystal property. A projected portion (2) is formed on a first major surface side of a semiconductor substrate (1). A first gate portion (3) having a width (length) smaller than that of the projected portion (2) is formed on the projected portion (2). An insulating layer (4) is formed on the whole surface of the semiconductor substrate (1) so as to bury the first gate portion (3). The semiconductor substrate (1) is removed horizontally from its second major surface side, i.e., from the opposite side of the side of the projected portion (2) to a position (a) at which the insulating layer (4) is formed so as to bury the projected portion (2) is exposed. A second gate portion (5) is formed on such exposed surface.

摘要翻译： 通过使用具有优异的晶体性质的半导体衬底，可以容易地制造横向绝缘栅型场效应晶体管。 突起部分（2）形成在半导体衬底（1）的第一主表面侧上。 在突出部分（2）上形成具有比突出部分（2）小的宽度（长度）的第一门部分（3）。 在半导体衬底（1）的整个表面上形成绝缘层（4），从而埋入第一栅极部分（3）。 半导体衬底（1）从其第二主表面侧，即从突出部分（2）的侧面的相对侧水平移除到形成绝缘层（4）的位置（a），从而 埋设投影部分（2）被暴露。 第二门部（5）形成在这样的暴露表面上。

公开(公告)号：US06274912B1

公开(公告)日：2001-08-14

申请号：US09177390

申请日：1998-10-23

申请人： Mikio Mukai ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Yutaka Hayashi

IPC分类号： H01L2976

CPC分类号： G11C11/405 ,  H01L27/108

摘要： A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control; the first transistor having source/drain regions constituted of a first region and a fourth region, and a channel forming region constituted of a surface region of a third region; the second transistor having source/drain regions constituted of a second region and the third region, and a channel forming region constituted of a surface region of the first region; the junction-field-effect transistor having gate regions constituted of the fifth region and a portion of the third region facing the fifth region, a channel region constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region, and source/drain regions constituted of the fourth region.

摘要翻译： 一种半导体存储单元，包括用于读出的第一导电类型的第一晶体管，用于写入的第二导电类型的第二晶体管和用于电流控制的第一导电类型的结场效应晶体管; 所述第一晶体管具有由第一区域和第四区域构成的源极/漏极区域，以及由第三区域的表面区域构成的沟道形成区域; 所述第二晶体管具有由第二区域和所述第三区域构成的源极/漏极区域，以及由所述第一区域的表面区域构成的沟道形成区域; 所述结场效应晶体管具有由所述第五区域和所述第三区域的与所述第五区域相对的部分构成的栅极区域，由所述第五区域和所述第三区域的所述部分夹持的所述第四区域的一部分构成的沟道区域， 以及由第四区域构成的源极/漏极区域。

公开(公告)号：US06240010B1

公开(公告)日：2001-05-29

申请号：US09511969

申请日：2000-02-23

申请人： Mikio Mukai ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Yutaka Hayashi

IPC分类号： G11C1136

CPC分类号： H01L27/11 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108

摘要： Provided is a semiconductor memory cell which requires no refreshing operation for retaining information. The semiconductor memory cell comprises a first transistor TR1 having a first conductivity type, a second transistor TR2 having a second conductivity type and a MIS type diode DT for retaining information, wherein one source/drain region of the first transistor TR1 corresponds to the channel forming region CH2 of the second transistor TR2, one source/drain region of the second transistor TR2 corresponds to the channel forming region CH1 of the first transistor TR1, one end of the MIS type diode DT is formed of an extending portion of the channel forming region CH1 of the first transistor TR1, and the other end of the MIS type diode DT is constituted of an electrode which is formed of an electrically conductive material and connected to a third line having a predetermined potential.

摘要翻译： 提供了不需要用于保留信息的刷新操作的半导体存储单元。 半导体存储单元包括具有第一导电类型的第一晶体管TR1，具有第二导电类型的第二晶体管TR2和用于保持信息的MIS型二极管DT，其中第一晶体管TR1的一个源极/漏极区对应于沟道形成 第二晶体管TR2的区域CH2，第二晶体管TR2的一个源极/漏极区域对应于第一晶体管TR1的沟道形成区域CH1，MIS型二极管DT的一端由沟道形成区域的延伸部分形成 第一晶体管TR1的CH1和MIS型二极管DT的另一端由由导电材料形成并连接到具有预定电位的第三线的电极构成。

公开(公告)号：US5563082A

公开(公告)日：1996-10-08

申请号：US362919

申请日：1994-12-23

申请人： Mikio Mukai

发明人： Mikio Mukai

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/20 ,  H01L21/302 ,  H01L21/76

CPC分类号： H01L29/7831 ,  H01L29/66772 ,  H01L29/66787

摘要： A method of manufacturing a lateral insulated gate field effect transistor comprises the steps of forming a projecting portion on a first major surface of a semiconductor substrate, forming a pair of gate portions each of which is formed in each side of the projecting portion, forming an insulating layer on the resulting surface of the semiconductor substrate by burying the projecting portion and the pair of gate portions, and removing the semiconductor substrate from a second major surface of the semiconductor substrate to a position of the insulating layer in which the projecting portion is buried to expose the bottom surface of the projecting portion.

摘要翻译： 制造横向绝缘栅场效应晶体管的方法包括以下步骤：在半导体衬底的第一主表面上形成突出部分，形成一对栅极部分，每个栅极部分形成在突出部分的每一侧，形成 通过埋入所述突出部分和所述一对栅极部分而在所述半导体衬底的所得表面上形成绝缘层，并且将所述半导体衬底从所述半导体衬底的第二主表面移除到所述绝缘层的位于所述绝缘层中的所述突出部分被埋置的位置 以暴露突出部分的底表面。

公开(公告)号：US06534812B1

公开(公告)日：2003-03-18

申请号：US09487919

申请日：2000-01-19

申请人： Mikio Mukai ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Yutaka Hayashi

IPC分类号： H01L27108

CPC分类号： H01L27/1203 ,  H01L27/108

摘要： A memory cell with a stored charge on its gate comprising; (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, (E) a first non-linear resistance element having two ends, one end being connected to the first gate, and (F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.

摘要翻译： 在其门上具有存储电荷的存储单元包括： （A）沟道形成区域，（B）形成在形成在沟道形成区域的表面上的绝缘层上的第一栅极，第一栅极和沟道形成区域通过绝缘层彼此面对，（C）第二栅极 与第一栅极电容耦合的栅极，（D）与沟道形成区域接触形成的源极/漏极区域，一个源极/漏极区域彼此间隔开，（E）具有两个端部的第一非线性电阻元件，一个 和（F）由第一栅极，绝缘层和沟道形成区域以及源极/漏极区域中的至少一个组成的第二非线性电阻元件。

公开(公告)号：US06501110B1

公开(公告)日：2002-12-31

申请号：US09552617

申请日：2000-04-19

申请人： Mikio Mukai ,  Toshio Kobayashi ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Toshio Kobayashi ,  Yutaka Hayashi

IPC分类号： H01L2976

CPC分类号： G11C11/405

摘要： A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

摘要翻译： 一种半导体存储单元，包括用于读出的第一晶体管，用于切换的第二晶体管，并且具有第一区域，形成在所述第一区域的表面区域中的第二区域，形成在所述第二区域的表面区域中的第三区域， 第四区域形成在第一区域的表面区域中并且与第二区域隔开，形成在第四区域的表面区域中的第五区域和栅极区域，其中当半导体存储单元被切割成第一虚拟垂直平面 其垂直于栅极区域的延伸方向并且通过栅极区域的中心，栅极区域附近的第二区域和第四区域相对于并联的第二假想垂直平面几乎对称 与栅极区域的延伸方向并通过栅极区域的中心。