公开(公告)号：US20120129287A1

公开(公告)日：2012-05-24

申请号：US13360838

申请日：2012-01-30

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01L33/08

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide, concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，硅或氧化硅，其连接到TFT的一侧的导电层的浓度范围为1原子％至6原子％，并且在含有机化合物的层的侧面上的硅或氧化硅浓度范围 从7原子％至15原子％。

公开(公告)号：US08129900B2

公开(公告)日：2012-03-06

申请号：US12239248

申请日：2008-09-26

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01J1/62 ,  H01J63/04 ,  H01J17/49

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，在与TFT连接的一侧上的导电层的硅或氧化硅浓度范围为1原子％至6原子％，并且在含有机化合物的层侧的硅或氧化硅浓度范围为 7原子％至15原子％。

公开(公告)号：US20050093432A1

公开(公告)日：2005-05-05

申请号：US10937904

申请日：2004-09-10

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： G09F9/30 ,  H01L27/32 ,  H01L51/50 ,  H01L51/52 ,  H05B33/10 ,  H05B33/26 ,  H05B33/28

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，在与TFT连接的一侧上的导电层的硅或氧化硅浓度范围为1原子％至6原子％，并且在含有机化合物的层侧的硅或氧化硅浓度范围为 7原子％至15原子％。

公开(公告)号：US08970106B2

公开(公告)日：2015-03-03

申请号：US13360838

申请日：2012-01-30

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01J1/62 ,  H01J63/04 ,  H01L51/52 ,  H01L27/32

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

公开(公告)号：US07492090B2

公开(公告)日：2009-02-17

申请号：US10937904

申请日：2004-09-10

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01J63/04 ,  H01J1/62 ,  H05B33/04

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，在与TFT连接的一侧上的导电层的硅或氧化硅浓度范围为1原子％至6原子％，并且在含有机化合物的层侧的硅或氧化硅浓度范围为 7原子％至15原子％。

公开(公告)号：US20090042326A1

公开(公告)日：2009-02-12

申请号：US12239248

申请日：2008-09-26

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01L33/00

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，在与TFT连接的一侧上的导电层的硅或氧化硅浓度范围为1原子％至6原子％，并且在含有机化合物的层侧的硅或氧化硅浓度范围为 7原子％至15原子％。

公开(公告)号：US20070034870A1

公开(公告)日：2007-02-15

申请号：US11582471

申请日：2006-10-17

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L31/00

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

摘要翻译： 在包括第一绝缘层，结晶半导体层和第二绝缘层的层叠体的半导体器件中，通过从应力平衡的角度来确定其结构，改善了器件的特性。 在包括在基板上具有拉伸应力的结晶半导体层的有源层的半导体器件中，对形成为与基板侧的半导体层的表面紧密接触的第一绝缘层施加拉伸应力，压缩应力 被赋予形成为与衬底侧相反的一侧与半导体层的表面紧密接触的第二绝缘层。

公开(公告)号：US07015505B2

公开(公告)日：2006-03-21

申请号：US10684936

申请日：2003-10-14

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

公开(公告)号：US06380558B1

公开(公告)日：2002-04-30

申请号：US09472137

申请日：1999-12-23

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L2904

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

摘要翻译： 在包括第一绝缘层，结晶半导体层和第二绝缘层的层叠体的半导体器件中，通过从应力平衡的角度来确定其结构，改善了器件的特性。 在包括在基板上具有拉伸应力的结晶半导体层的有源层的半导体器件中，对形成为与基板侧的半导体层的表面紧密接触的第一绝缘层施加拉伸应力，压缩应力 被赋予形成为与衬底侧相反的一侧与半导体层的表面紧密接触的第二绝缘层。

公开(公告)号：US07476577B2

公开(公告)日：2009-01-13

申请号：US11582471

申请日：2006-10-17

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/20

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.