公开(公告)号：US20090119450A1

公开(公告)日：2009-05-07

申请号：US12265324

申请日：2008-11-05

申请人： Shusuke SAEKI ,  Satoru Iwasaki ,  Seiya Ichimori ,  Hiroki Nagahama ,  Kazumi Sato

发明人： Shusuke SAEKI ,  Satoru Iwasaki ,  Seiya Ichimori ,  Hiroki Nagahama ,  Kazumi Sato

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7209

摘要： A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size.

摘要翻译： 存储装置包括非易失性存储器，其允许电子地写入，读取和擦除数据，并且以页面为单位进行写入和读取，并且以包括多个页面的块为单位进行擦除;以及 管理对非易失性存储器的访问的控制部分。 控制部分通过以平移单元（TU）为单位的逻辑地址 - 物理地址转换（逻辑 - 物理转换）来执行对非易失性存储器的访问的管理，每个转换单元（TU）是块大小的整数个分数， 页面大小。

公开(公告)号：US08205033B2

公开(公告)日：2012-06-19

申请号：US12265324

申请日：2008-11-05

申请人： Shusuke Saeki ,  Satoru Iwasaki ,  Seiya Ichimori ,  Hiroki Nagahama ,  Kazumi Sato

发明人： Shusuke Saeki ,  Satoru Iwasaki ,  Seiya Ichimori ,  Hiroki Nagahama ,  Kazumi Sato

IPC分类号： G06F12/00 ,  G11C16/02

CPC分类号： G06F12/0246 ,  G06F2212/7209

摘要： A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size.

摘要翻译： 存储装置包括非易失性存储器，其允许电子地写入，读取和擦除数据，并且以页面为单位进行写入和读取，并且以包括多个页面的块为单位进行擦除;以及 管理对非易失性存储器的访问的控制部分。 控制部分通过以平移单元（TU）为单位的逻辑地址 - 物理地址转换（逻辑 - 物理转换）来执行对非易失性存储器的访问的管理，每个转换单元（TU）是块大小的整数个分数， 页面大小。

公开(公告)号：US20120297151A1

公开(公告)日：2012-11-22

申请号：US13465448

申请日：2012-05-07

申请人： Hiroki KAMINAGA ,  Seiya Ichimori ,  Katsuya Takahashi ,  Yoriko Komatsuzaki ,  Masahiro Tamori

发明人： Hiroki KAMINAGA ,  Seiya Ichimori ,  Katsuya Takahashi ,  Yoriko Komatsuzaki ,  Masahiro Tamori

IPC分类号： G06F12/00

CPC分类号： G06F9/5016 ,  G06F9/5022 ,  G06F12/023 ,  G06F12/08 ,  G06F12/12 ,  G06F2209/504 ,  Y02D10/22

摘要： If it is determined in step S51 that allocation for an instruction part has been requested and it is determined in step S52 that a memory use amount of an instruction part of an allocation target program exceeds an upper limit, a memory area that is being used by the instruction part of the allocation target program is released in step S53 and memory allocation for the instruction part is performed in step S54. If it is determined in step S52 that the memory use amount of the instruction part of the allocation target program does not exceed the upper limit, the process in step S53 is skipped. If it is determined in step S51 that allocation for a data part is requested, a normal memory allocation process is performed in step S55. The present disclosure may be applied to, for example, an embedded device.

摘要翻译： 如果在步骤S51中确定已经请求了指令部分的分配，并且在步骤S52中确定分配目标程序的指令部分的存储器使用量超过上限，则由 在步骤S53解除分配目标程序的指令部分，并且在步骤S54中执行指令部分的存储器分配。 如果在步骤S52中确定分配目标程序的指令部分的存储器使用量不超过上限，则跳过步骤S53中的处理。 如果在步骤S51中确定请求了对数据部分的分配，则在步骤S55中执行正常的存储器分配处理。 本公开可以应用于例如嵌入式设备。