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1.发明授权Integrated circuit system employing multiple exposure dummy patterning technology 有权采用多次曝光虚拟图形化技术的集成电路系统公开(公告)号：US08003311B2
公开(公告)日：2011-08-23
申请号：US11972809
申请日：2008-01-11
申请人： Sia Kim Tan , Soo Muay Goh , Qunying Lin , Martin Yeo
发明人： Sia Kim Tan , Soo Muay Goh , Qunying Lin , Martin Yeo
IPC分类号： G03F7/20
CPC分类号： H01L21/31144 , G03F1/36 , G03F7/70466 , H01L21/76816 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate coated with a photoresist material; exposing the photoresist material to an energy source through a first mask to form a first substrate feature and a second substrate feature therein; and exposing the photoresist material to the energy source through a second mask to transform the second substrate feature into another one of the first substrate feature therein.
摘要翻译： 一种集成电路系统，包括：提供涂覆有光致抗蚀剂材料的基底; 通过第一掩模将光致抗蚀剂材料暴露于能量源以在其中形成第一衬底特征和第二衬底特征; 以及通过第二掩模将所述光致抗蚀剂材料暴露于所述能量源，以将所述第二衬底特征变换为所述第一衬底特征中的另一衬底特征。
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2.发明申请INTEGRATED CIRCUIT SYSTEM EMPLOYING MULTIPLE EXPOSURE DUMMY PATTERNING TECHNOLOGY 有权集成电路系统采用多种曝光方式绘图技术公开(公告)号：US20090181551A1
公开(公告)日：2009-07-16
申请号：US11972809
申请日：2008-01-11
申请人： Sia Kim Tan , Soo Muay Goh , Qunying Lin , Martin Yeo
发明人： Sia Kim Tan , Soo Muay Goh , Qunying Lin , Martin Yeo
IPC分类号： H01L21/30
CPC分类号： H01L21/31144 , G03F1/36 , G03F7/70466 , H01L21/76816 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate coated with a photoresist material; exposing the photoresist material to an energy source through a first mask to form a first substrate feature and a second substrate feature therein; and exposing the photoresist material to the energy source through a second mask to transform the second substrate feature into another one of the first substrate feature therein.
摘要翻译： 一种集成电路系统，包括：提供涂覆有光致抗蚀剂材料的基底; 通过第一掩模将光致抗蚀剂材料暴露于能量源以在其中形成第一衬底特征和第二衬底特征; 以及通过第二掩模将所述光致抗蚀剂材料暴露于所述能量源，以将所述第二衬底特征变换为所述第一衬底特征中的另一衬底特征。
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3.发明申请INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF 有权具有子几何去除的集成电路系统及其制造方法公开(公告)号：US20090309192A1
公开(公告)日：2009-12-17
申请号：US12477448
申请日：2009-06-03
申请人： Soon Yoeng Tan , Huey Ming Chong , Byoung-IL Choi , Soo Muay Goh
发明人： Soon Yoeng Tan , Huey Ming Chong , Byoung-IL Choi , Soo Muay Goh
CPC分类号： G03F1/36
摘要： A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.
摘要翻译： 一种集成电路系统的制造方法，包括：形成掩模版数据; 在掩模版数据中检测子几何，奇点或其组合; 应用单元，补片或其组合以从掩模版数据中去除子几何，奇点或其组合; 并从掩模版数据制造集成电路。
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4.发明授权Integrated circuit system with sub-geometry removal and method of manufacture thereof 有权具有子几何去除的集成电路系统及其制造方法公开(公告)号：US08293546B2
公开(公告)日：2012-10-23
申请号：US12477448
申请日：2009-06-03
申请人： Soon Yoeng Tan , Huey Ming Chong , Byoung-Il Choi , Soo Muay Goh
发明人： Soon Yoeng Tan , Huey Ming Chong , Byoung-Il Choi , Soo Muay Goh
IPC分类号： H01L21/66
CPC分类号： G03F1/36
摘要： A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.
摘要翻译： 一种集成电路系统的制造方法，包括：形成掩模版数据; 在掩模版数据中检测子几何，奇点或其组合; 应用单元，补片或其组合以从掩模版数据中去除子几何，奇点或其组合; 并从掩模版数据制造集成电路。
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