公开(公告)号：US4124088A

公开(公告)日：1978-11-07

申请号：US713813

申请日：1976-08-12

Applicant: Sigeru Kuriyama ,  Minoru Kaminaga

Inventor： Sigeru Kuriyama ,  Minoru Kaminaga

IPC: H02P3/08 ,  B60L7/00 ,  B60L15/20 ,  H02P3/10 ,  B60K31/00 ,  B60T8/08

CPC classification number: B60L7/006 ,  B60L15/2009 ,  H02P3/10 ,  B60L2270/145 ,  Y02T10/645 ,  Y02T10/7275

Abstract: A velocity at the time when the accelerator of a vehicle is released is stored under a certain condition in advance, and the stored vehicle velocity and an actual vehicle velocity are compared. When the actual vehicle velocity becomes greater than the stored vehicle velocity by a predetermined value, the downward inclination of a running road surface is regarded as exceeding a predetermined value, and safety means such as a brake is driven. As compared with a case of employing an inclination angle sensor such as a mercury switch, the device operates accurately without being influenced by a change in the vibration or acceleration of the vehicle.

Abstract translation: 在车辆的加速器被释放时的速度预先存储在一定条件下，并且比较存储的车速和实际车速。 当实际车速大于存储的车速达预定值时，行驶路面的向下倾斜被认为超过预定值，并且驱动诸如制动器的安全装置。 与使用诸如水银开关的倾斜角传感器的情况相比，该装置精确地操作，而不受车辆的振动或加速度的变化的影响。

公开(公告)号：US06552551B2

公开(公告)日：2003-04-22

申请号：US09878352

申请日：2001-06-12

Applicant: Michio Komoda ,  Sigeru Kuriyama

Inventor： Michio Komoda ,  Sigeru Kuriyama

IPC: G01R2726

CPC classification number: G01R31/2882 ,  G01R31/3191 ,  G01R31/31937

Abstract: In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.

公开(公告)号：US4079270A

公开(公告)日：1978-03-14

申请号：US681248

申请日：1976-04-28

Applicant: Masahiko Ibamoto ,  Masato Suzuki ,  Sigeru Kuriyama

Inventor： Masahiko Ibamoto ,  Masato Suzuki ,  Sigeru Kuriyama

IPC: G05F1/10 ,  H02M1/06 ,  H02M1/08 ,  H02M3/137 ,  H03K17/60

CPC classification number: H02M3/137

Abstract: In a semiconductor device which includes a main thyristor and an auxiliary thyristor for turning off the main thyristor and controls conduction period of the main thyristor according to a given duty factor, a gate control apparatus comprising a phase shifter for producing a square wave output corresponding to the duty factor, an integrator for integrating the output of the phase shifter, a relay circuit having two level settings and receiving the output from the integrator to produce an output which exhibits a hysterisis characteristic corresponding to the two level settings, and an amplifier for turning on the main thyristor in response to the output from the relay circuit and turning on the auxiliary thyristor upon the termination of the output from the relay circuit.

Abstract translation: 在包括用于关断主晶闸管的主晶闸管和辅助晶闸管的半导体器件中，根据给定的占空因数控制主晶闸管的导通周期，门控制装置包括用于产生对应于 占空因数，用于积分移相器的输出的积分器，具有两个电平设置的继电器电路并且接收来自积分器的输出以产生表现出与两个电平设置相对应的滞后特性的输出，以及用于转动的放大器 在主晶闸管上响应于继电器电路的输出并在继电器电路的输出终止时接通辅助晶闸管。