公开(公告)号：US11959964B2

公开(公告)日：2024-04-16

申请号：US18328715

申请日：2023-06-02

申请人： SEMITRONIX CORPORATION

发明人： Jiabai Cheng ,  Wei Chen ,  Ludan Yang ,  Fan Lan

IPC分类号： G01R31/28 ,  G01R31/317

CPC分类号： G01R31/31722 ,  G01R31/2882 ,  G01R31/2886

摘要： A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

公开(公告)号：US20230324458A1

公开(公告)日：2023-10-12

申请号：US18328715

申请日：2023-06-02

申请人： SEMITRONIX CORPORATION

发明人： Jiabai CHENG ,  Wei CHEN ,  Ludan YANG ,  Fan LAN

IPC分类号： G01R31/28 ,  G01R31/317

CPC分类号： G01R31/31722 ,  G01R31/2882 ,  G01R31/2886

摘要： A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

公开(公告)号：US20180180667A1

公开(公告)日：2018-06-28

申请号：US15390505

申请日：2016-12-25

申请人： NUVOTON TECHNOLOGY CORPORATION

发明人： Josef Nevo ,  Alain Bismuth ,  Ilan Margalit

IPC分类号： G01R31/28

CPC分类号： G01R31/2882 ,  G01R31/2834

摘要： A method of testing an integrated circuit device, which involves receiving, by a processor, a test definition indicating a sequence of acts to be performed by an automated test equipment in testing an integrated circuit device. The test definition includes indications of test cycles and timings of events in the cycles. The method includes scanning the received test definition, by the processor, for switch time points for which a timing of events in a first cycle immediately preceding the switch time point is different from a timing of events in a second cycle immediately following the switch time point, determining problematic switch time points for which the combined rest duration from a specific event in the first cycle to a corresponding specific event in the second cycle is shorter than a minimal switch period of the automated test equipment, changing the received test definition by extending a length of the cycles immediately preceding the determined problematic switch time points and providing the changed test definition for testing the integrated circuit device by the automated test equipment.

公开(公告)号：US09899993B2

公开(公告)日：2018-02-20

申请号：US14913309

申请日：2014-07-29

申请人： JAPAN SCIENCE AND TECHNOLOGY AGENCY

发明人： Hidetoshi Onodera ,  Islam A. K. M Mahfuzul

IPC分类号： H03K5/134 ,  G01R31/28 ,  H03K5/00

CPC分类号： H03K5/134 ,  G01R31/2882 ,  H03K2005/00019

摘要： A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.

公开(公告)号：US09865486B2

公开(公告)日：2018-01-09

申请号：US15083692

申请日：2016-03-29

申请人： GLOBALFOUNDRIES INC.

发明人： Igor Arsovski ,  Jeanne P. Bickford ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger ,  Jeanne H. Raymond

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/67 ,  G06F17/50 ,  G01R31/28

CPC分类号： H01L21/67271 ,  G01R31/2882 ,  G01R31/3004 ,  G01R31/31718 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/10 ,  G06F2217/78 ,  G06F2217/84 ,  H01L21/67253 ,  H01L22/14

摘要： Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified.

公开(公告)号：US09618571B2

公开(公告)日：2017-04-11

申请号：US14436605

申请日：2013-09-22

申请人： ZTE CORPORATION

发明人： Yongbo Zhang

IPC分类号： G01R31/28 ,  G01R19/10

CPC分类号： G01R31/2882 ,  G01R19/10

摘要： A detection circuit for a relative error voltage, including: a first current mirror, a second current mirror, a third current mirror, a current sink and resistors R1, R2 and R3. A voltage signal to be detected V1 accesses the first current mirror via the resistor R2, and a voltage signal to be detected V2 accesses the second current mirror via the resistor R3; a mirrored-end of the first current mirror is connected to the current sink, and a mirroring-end thereof is connected to a mirrored-end of the third current mirror; a mirrored-end of the second current mirror is connected to the current sink, and a mirroring-end thereof is connected to a mirroring-end of the third current mirror; the current sink is grounded via the resistor R1; and the third current mirror converts double-ended currents of the first and the second current mirrors to single-ended currents to output as voltage signals.

公开(公告)号：US09541605B1

公开(公告)日：2017-01-10

申请号：US14969659

申请日：2015-12-15

申请人： International Business Machines Corporation

发明人： Chandrasekharan Kothandaraman

IPC分类号： G01R27/28 ,  G01R31/327 ,  H03K3/03 ,  G01R31/28

CPC分类号： G01R31/3277 ,  G01R31/2882 ,  G01R31/3278 ,  G11C11/16 ,  G11C29/08 ,  H03K3/0315 ,  H03K3/59

摘要： Circuits are provided for modeling and characterizing the switching of magnetic tunnel junctions (MTJ) elements. More specifically, ring oscillators loaded with MTJ elements are used to characterize magnetic tunnel junction (MTJ) element performance. The circuits can include a ring oscillator (RO) having an odd number of inverters connected in series with a magnetic tunnel junction (MTJ) element inserted between each inverter. In some embodiments, the magnetic tunnel junction (MTJ) elements are arranged to act as a load to the inverters. The circuits optionally include one or more of a time to amplitude converter, a pulse distribution analyzer and/or PFET(s) and NFET(s). Methods of characterizing the switching characteristics of MTJ elements are also provided herein. Such MTJ elements can be suitable for use in magnetoresistive random access memory (MRAM) devices. Methods of making the ring oscillator are further provided herein.

摘要翻译： 提供电路用于建模和表征磁隧道结（MTJ）元件的切换。 更具体地说，装载有MTJ元件的环形振荡器用于表征磁性隧道结（MTJ）元件性能。 电路可以包括具有与插入在每个逆变器之间的磁性隧道结（MTJ）元件串联连接的奇数个反相器的环形振荡器（RO）。 在一些实施例中，磁性隧道结（MTJ）元件被布置成充当逆变器的负载。 电路可选地包括时间到振幅转换器，脉冲分布分析器和/或PFET和NFET中的一个或多个。 本文还提供了MTJ元件的开关特性的表征方法。 这样的MTJ元件可以适用于磁阻随机存取存储器（MRAM）装置。 本文进一步提供制造环形振荡器的方法。

公开(公告)号：US20160111399A1

公开(公告)日：2016-04-21

申请号：US14981284

申请日：2015-12-28

申请人： SK hynix Inc.

发明人： Tae Sik YUN ,  Sang Jin BYEON

IPC分类号： H01L25/065 ,  H03K17/14

CPC分类号： H01L25/0657 ,  G01R31/2882 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H03K17/14 ,  H03K19/00369 ,  Y10T307/826

摘要： A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the to replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed is through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

摘要翻译： 半导体装置包括：从芯片，包括信号传送单元，配置为响应于芯片选择信号确定是否传送输入信号; 包括具有与信号传送单元相同的配置的复制电路单元的主芯片和被配置为接收信号传送单元的输出信号和复制电路单元的输出信号的信号输出单元，并响应于响应而产生输出信号 到控制信号; 通过垂直形成的从芯片的第一通芯片，并且一端连接到主芯片以接收输入信号，另一端连接到信号传送单元; 并且垂直形成的第二通芯片通过从芯片，并且其一端连接到信号传送单元，另一端连接到信号输出单元。

公开(公告)号：US09183333B2

公开(公告)日：2015-11-10

申请号：US13965107

申请日：2013-08-12

申请人： Synopsys, Inc.

发明人： Ahmed M. Shebaita

IPC分类号： G06F17/50 ,  G06F11/22 ,  G06F9/455 ,  G01R31/28

CPC分类号： G06F17/5045 ,  G01R31/2882 ,  G01R31/2894 ,  G06F17/5031 ,  G06F17/5068 ,  G06F2217/84

摘要： A method and apparatus of a device that performs a generalized moment based variation aware timing analysis on a circuit design is described. The device receives a signal path that traverses a plurality of gates. For each of the plurality of gates, the device retrieves a statistical distribution that represents delay variation at the gate. The statistical distribution for each gate is measured by a number of statistical moments that include higher order statistical moments besides the mean and the standard deviation of the distribution. The device computes statistical moments to represent the timing variation on the signal path by propagating statistical distributions of the gates on the signal path. The device reconstructs a statistical distribution function for timing variation on the signal path based on the computed statistical moments.

摘要翻译： 描述了在电路设计上执行基于广义力矩的变化感知时序分析的装置的方法和装置。 该装置接收穿过多个门的信号路径。 对于多个门中的每一个，设备检索表示门处的延迟变化的统计分布。 每个门的统计分布通过除了平均值和分布的标准偏差之外的包括更高阶统计矩的多个统计矩测量。 该装置通过传播信号路径上的门的统计分布来计算统计矩，以表示信号路径上的定时变化。 该装置基于计算出的统计矩，重建用于信号路径上的定时变化的统计分布函数。

公开(公告)号：US09050017B2

公开(公告)日：2015-06-09

申请号：US13555616

申请日：2012-07-23

申请人： Tak-Shing Ching ,  Tai-Ping Sun ,  Chia-Ming Liu

发明人： Tak-Shing Ching ,  Tai-Ping Sun ,  Chia-Ming Liu

IPC分类号： A61B5/053 ,  G01R31/28 ,  G01R27/26

CPC分类号： A61B5/053 ,  G01R27/26 ,  G01R31/2882

摘要： An impedance analyzer includes: a control voltage generating unit for generating a control voltage that has a predetermined amplitude value; a measuring unit operable to provide an output current, which has an amplitude value corresponding to that of the control voltage, for flowing through first and second body portions of a biological target, and to generate a measurement voltage that has an amplitude value corresponding to a difference between voltages at the first and second body portions attributed to flow of the output current therethrough; and a calculating module operable to determine an electrical impedance between the first and second body portions according to a predetermined adjustment value and the amplitude value of the measurement voltage.

摘要翻译： 阻抗分析器包括：用于产生具有预定振幅值的控制电压的控制电压产生单元; 测量单元，其可操作以提供具有对应于所述控制电压的振幅值的输出电流，用于流过生物靶的第一和第二主体部分，并且产生具有对应于生物靶的振幅值的测量电压 由于输出电流流过其中的第一和第二主体部分的电压之差; 以及计算模块，其可操作以根据预定的调整值和所述测量电压的振幅值来确定所述第一和第二主体部分之间的电阻抗。