公开(公告)号：US11012055B2

公开(公告)日：2021-05-18

申请号：US16415054

申请日：2019-05-17

申请人： Silego Technology Inc.

发明人： Vikas Vinayak ,  David Kuneth Chow ,  Nathan Willis John ,  Sidney Chan

IPC分类号： H03K3/0233 ,  H03K5/1534 ,  H02M1/08 ,  H02M3/158 ,  H03K19/20 ,  H03K5/00

摘要： A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.