Integrated user programmable slew-rate controlled soft-start for LDO

    公开(公告)号:US11914409B2

    公开(公告)日:2024-02-27

    申请号:US17564947

    申请日:2021-12-29

    发明人: Hua Zhu

    IPC分类号: G05F1/575 G05F1/46

    CPC分类号: G05F1/575 G05F1/468

    摘要: Disclosed is an integrated user programmable slew-rate controlled soft-start for a low-dropout regulator that includes a current steering stage and an integrator stage. The current steering stage may also be denoted as an error amplifier. A Miller compensation capacitor couples between an input node to the integrator stage and an output node for an output voltage of LDO. During a power up period of the LDO, the current steering stage generates an input current that charges the Miller compensation capacitor. This controlled charging of the Miller compensation capacitor controls the slew rate of the output voltage as it rises to its regulated value at a completion of the power up period.

    Packaging Substrate
    2.
    发明公开
    Packaging Substrate 审中-公开

    公开(公告)号:US20230335511A1

    公开(公告)日:2023-10-19

    申请号:US18340366

    申请日:2023-06-23

    IPC分类号: H01L23/64 H01L23/498

    摘要: A packaging substrate and a method for mounting an integrated circuit and/or a circuit component is presented. The packaging substrate includes an upper surface for mounting the integrated circuit and/or circuit component; a lower surface opposite to the upper surface, wherein the lower surface is for mounting to a printed circuit board (PCB); a non-conductive material; wherein the non-conductive material is a plastic: an inductor structure at least partially embedded in the non-conductive material; first and second conductive materials, and conductive pillars, arranged to form a first coil and a second coil having an inductance; wherein the first coil and second coil are arranged as a toroid transformer wound in a double helix configuration.

    Differential Amplifier
    3.
    发明申请

    公开(公告)号:US20220103128A1

    公开(公告)日:2022-03-31

    申请号:US17484069

    申请日:2021-09-24

    IPC分类号: H03F1/02 H03F3/45

    摘要: The present document relates to differential amplifiers. A differential amplifier may comprise a current source, a first transistor, a second transistor, and a compensation circuit. A reference voltage may be applied to a first terminal of the first transistor, and a second terminal of the first transistor may be coupled to an output of the current source. A feedback voltage may be applied to a first terminal of the second transistor, and a second terminal of the second transistor may be coupled to the output of the current source. The compensation circuit may comprise a capacitive element coupled to the first terminal of the first transistor, and the compensation circuit may be configured to reduce a change of the reference voltage at the first terminal of the first transistor.

    PFM controller for a multi-level converter utilizing flying capacitor voltage monitors

    公开(公告)号:US11165344B2

    公开(公告)日:2021-11-02

    申请号:US16731721

    申请日:2019-12-31

    IPC分类号: H02M3/07

    摘要: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter comprises a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage-level controller. The MLDC converter includes the IMPM and the IMPM includes the flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor and the voltage-level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor and switches a state of operation of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.

    PFM CONTROLLER FOR A MULTI-LEVEL CONVERTER UTILIZING FLYING CAPACITOR VOLTAGE MONITORS

    公开(公告)号:US20210203223A1

    公开(公告)日:2021-07-01

    申请号:US16731721

    申请日:2019-12-31

    IPC分类号: H02M3/07

    摘要: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter comprises a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage-level controller. The MLDC converter includes the IMPM and the IMPM includes the flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor and the voltage-level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor and switches a state of operation of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.

    Contactless encoder
    6.
    发明授权

    公开(公告)号:US10782158B1

    公开(公告)日:2020-09-22

    申请号:US16138240

    申请日:2018-09-21

    发明人: Jozef Froniewski

    IPC分类号: G01D5/241 H01H19/14 G01D5/249

    摘要: A contactless encoder is disclosed. The encoder comprises a selector configured to select one of a plurality of states associated with the encoder. The encoder furthermore comprises an integrated circuit comprising a finite state machine configured to detect a currently selected state by the selector and generate an output signal corresponding to the detected currently selected state, wherein the currently selected state is detected based on a capacitive coupling between the selector and a portion of the encoder associated with the currently selected state.

    INTEGRATED CIRCUIT FREQUENCY GENERATOR
    7.
    发明申请
    INTEGRATED CIRCUIT FREQUENCY GENERATOR 审中-公开
    集成电路频率发生器

    公开(公告)号:US20150288372A1

    公开(公告)日:2015-10-08

    申请号:US14726308

    申请日:2015-05-29

    IPC分类号: H03L7/24 H03B5/32

    摘要: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

    摘要翻译: 公开了一种集成电路频率发生器。 在一些实施例中,频率发生器包括被配置为产生振荡器频率的电子振荡器和被配置为相对于参考频率源周期性地校准电子振荡器的校准电路。 当主电源不可用时,从振荡器频率产生输出频率,并且仅在校准周期内引用参考频率源。

    INTEGRATED USER PROGRAMMABLE SLEW-RATE CONTROLLED SOFT-START FOR LDO

    公开(公告)号:US20230205245A1

    公开(公告)日:2023-06-29

    申请号:US17564947

    申请日:2021-12-29

    发明人: Hua Zhu

    IPC分类号: G05F1/575 G05F1/46

    CPC分类号: G05F1/575 G05F1/468

    摘要: Disclosed is an integrated user programmable slew-rate controlled soft-start for a low-dropout regulator that includes a current steering stage and an integrator stage. The current steering stage may also be denoted as an error amplifier. A Miller compensation capacitor couples between an input node to the integrator stage and an output node for an output voltage of LDO. During a power up period of the LDO, the current steering stage generates an input current that charges the Miller compensation capacitor. This controlled charging of the Miller compensation capacitor controls the slew rate of the output voltage as it rises to its regulated value at a completion of the power up period.

    Comparator system
    9.
    发明授权

    公开(公告)号:US11012055B2

    公开(公告)日:2021-05-18

    申请号:US16415054

    申请日:2019-05-17

    摘要: A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.