公开(公告)号：US20210365100A1

公开(公告)日：2021-11-25

申请号：US17395311

申请日：2021-08-05

Applicant: Silicon Laboratories Inc.

Inventor： Partha Sarathy MURALI ,  Suryanarayana Varma NALLAPARAJU ,  Kriyangbhai Vinodbhai SHAH ,  Venkata Rao GUNTURU ,  Subba Reddy KALLAM ,  Mani Kumar KOTHAMASU

IPC: G06F1/3237 ,  G06F1/3296 ,  H04W52/02 ,  G06F1/3209

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.