公开(公告)号：US11320482B2

公开(公告)日：2022-05-03

申请号：US16801447

申请日：2020-02-26

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Raghavendra Pai Kateel ,  HengWee Cheng ,  Anil Shirwaikar

IPC: G01R31/3177 ,  G01R31/317 ,  G06F21/74 ,  G01R31/327

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

公开(公告)号：US20210263098A1

公开(公告)日：2021-08-26

申请号：US16801447

申请日：2020-02-26

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Raghavendra Pai Kateel ,  HengWee Cheng ,  Anil Shirwaikar

IPC: G01R31/3177 ,  G06F21/74 ,  G01R31/317

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

公开(公告)号：US10222421B1

公开(公告)日：2019-03-05

申请号：US15896678

申请日：2018-02-14

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Raghavendra Pai Kateel ,  Shantonu Bhadury

IPC: G01R31/3185 ,  G01R31/10 ,  G01R31/28 ,  G01R31/3177

Abstract: Embodiments are disclosed for systems and methods that include pulsing a clock pin of retention cells included within a scan chain to shift a sequence of logic values into the scan chain, so that successive cells are loaded with opposite logic values. Embodiments also include pulsing a retain pin to retain the logic values, and pulsing the clock pin to shift the sequence of logic values through the chain, so that retained logic values are output from, and logic values opposite to the retained logic values are loaded into, the cells. Embodiments also include pulsing a restore pin to restore the retained logic values, pulsing the clock pin to shift the logic values out of the scan chain, comparing the logic values shifted out of the scan chain with the logic values shifted into the scan chain, and detecting a fault on the retain pin based on said comparison.