公开(公告)号：US20210263098A1

公开(公告)日：2021-08-26

申请号：US16801447

申请日：2020-02-26

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Raghavendra Pai Kateel ,  HengWee Cheng ,  Anil Shirwaikar

IPC: G01R31/3177 ,  G06F21/74 ,  G01R31/317

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

公开(公告)号：US20220129166A1

公开(公告)日：2022-04-28

申请号：US17078224

申请日：2020-10-23

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Anil Shirwaikar ,  Yu Zhou

IPC: G06F3/06

Abstract: In one aspect, an apparatus includes a memory repair controller coupled to a memory. The memory repair controller may be configured to provide repair information to cause the memory to disable one or more faulty locations in the memory, and the memory repair controller can be disabled after providing the repair information.

公开(公告)号：US11320482B2

公开(公告)日：2022-05-03

申请号：US16801447

申请日：2020-02-26

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Raghavendra Pai Kateel ,  HengWee Cheng ,  Anil Shirwaikar

IPC: G01R31/3177 ,  G01R31/317 ,  G06F21/74 ,  G01R31/327

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

公开(公告)号：US11579776B2

公开(公告)日：2023-02-14

申请号：US17078224

申请日：2020-10-23

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Anil Shirwaikar ,  Yu Zhou

IPC: G06F3/06 ,  G11C29/00 ,  G11C29/04

Abstract: In one aspect, an apparatus includes a memory repair controller coupled to a memory. The memory repair controller may be configured to provide repair information to cause the memory to disable one or more faulty locations in the memory, and the memory repair controller can be disabled after providing the repair information.

公开(公告)号：US11323029B2

公开(公告)日：2022-05-03

申请号：US16857901

申请日：2020-04-24

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elkholy ,  Anil Shirwaikar

IPC: H02M3/158 ,  H02M1/088 ,  H02M1/32 ,  H02M1/44 ,  H02M1/14 ,  H04B1/40 ,  H02M1/00

Abstract: A DC-DC converter including converter circuitry, a voltage detector providing a low voltage signal, and pulse-pairing circuitry. The converter circuitry may be configured according to a buck or a boost configuration switching between a zero and peak current levels. The pulse-pairing circuitry includes a paired pulse generator, a load detector, and a maximum on timing controller. In response to the low voltage signal, the paired pulse generator activates an on signal for a pair of equal duration on pulses separated by a predetermined pulse separation interval. The on time periods are based on an adjustable time value and a peak current indication. The load detector provides a load adjust signal for adjusting the time value based on sampling the low voltage signal and an off time signal at the start of the second pulse. The maximum on timing controller adjusts the adjustable time value based on the load adjust signal.

公开(公告)号：US20210336539A1

公开(公告)日：2021-10-28

申请号：US16857901

申请日：2020-04-24

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elkholy ,  Anil Shirwaikar

IPC: H02M3/158 ,  H02M1/088

Abstract: A DC-DC converter including converter circuitry, a voltage detector providing a low voltage signal, and pulse-pairing circuitry. The converter circuitry may be configured according to a buck or a boost configuration switching between a zero and peak current levels. The pulse-pairing circuitry includes a paired pulse generator, a load detector, and a maximum on timing controller. In response to the low voltage signal, the paired pulse generator activates an on signal for a pair of equal duration on pulses separated by a predetermined pulse separation interval. The on time periods are based on an adjustable time value and a peak current indication. The load detector provides a load adjust signal for adjusting the time value based on sampling the low voltage signal and an off time signal at the start of the second pulse. The maximum on timing controller adjusts the adjustable time value based on the load adjust signal.