公开(公告)号：US20210076248A1

公开(公告)日：2021-03-11

申请号：US16945870

申请日：2020-08-02

Applicant: Silicon Laboratories Inc.

Inventor： Subba Reddy KALLAM ,  Partha MURALI ,  Venkat MATTELA ,  Venkata Siva Prasad PULAGAM

IPC: H04W28/02 ,  H04W72/06 ,  H04W72/08 ,  H04W16/18 ,  H04W84/12 ,  H04W4/80 ,  G06F9/38 ,  G06F9/30

Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

公开(公告)号：US20240397368A1

公开(公告)日：2024-11-28

申请号：US18765347

申请日：2024-07-08

Applicant: Silicon Laboratories Inc

Inventor： Subba Reddy KALLAM ,  Partha Sarathy MURALI ,  Venkat MATTELA ,  Venkata Siva Prasad PULAGAM

IPC: H04W28/02 ,  G06F9/30 ,  G06F9/38 ,  H04W4/80 ,  H04W16/18 ,  H04W72/54 ,  H04W72/563 ,  H04W84/12

Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

公开(公告)号：US20210073027A1

公开(公告)日：2021-03-11

申请号：US16945871

申请日：2020-08-02

Applicant: Silicon Laboratories Inc.

Inventor： Subba Reddy KALLAM ,  Partha Sarathy MURALI ,  Venkat MATTELA ,  Venkata Siva Prasad PULAGAM

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  H04W4/80 ,  H04W12/06 ,  H04W80/04 ,  H04W80/02 ,  H04L12/861 ,  H04L29/06

Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.