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公开(公告)号：US10944388B1
公开(公告)日：2021-03-09
申请号：US16710365
申请日：2019-12-11
Applicant: Silicon Laboratories Inc.
Inventor： Chester Yu , Y Hao Lim
Abstract: Improved clock gating cells and related methods are provided. The clock gating cells include a first mutually exclusive element (ME1), a first inverter and a second mutually exclusive element (ME2). ME1 receives a clock input and an enable signal, which is asynchronous to the clock input, and outputs the enable signal based on a timing relationship between the clock input and the enable signal. The first inverter receives the enable signal output from ME1 and provides an inverted enable signal to ME2. ME2 receives the clock input and the inverted enable signal, and provides a clock output based on a timing relationship between the clock input and the inverted enable signal. Together, ME1 and ME2 resolve meta-stability and eliminate glitches in the clock output by preventing rising and falling edges of the enable signal from passing through the mutually exclusive elements during active phases of the clock input.
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