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公开(公告)号:US12260121B2
公开(公告)日:2025-03-25
申请号:US18202962
申请日:2023-05-29
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
Abstract: A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, the flash memory device comprising an input/output (I/O) control circuit, a command register, an address register, a memory cell array at least having a first plane and a second plane which is different from the first plane, at least one address decoder, and a control circuit having a specific buffer, and the method comprises: buffering command information of a command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the command register; buffering address information of the command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the address register; and controlling the specific buffer storing a transmission history information of the specific communication interface.
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公开(公告)号:US20240402937A1
公开(公告)日:2024-12-05
申请号:US18203066
申请日:2023-05-30
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is coupled to the flash memory device through the specific communication interface, and used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array and to make the flash memory device determine whether the multiple page units are empty pages.
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公开(公告)号:US12112816B2
公开(公告)日:2024-10-08
申请号:US18094989
申请日:2023-01-10
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G11C29/12
CPC classification number: G11C29/12005 , G11C29/1201
Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection access command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the error injection access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with controlling a memory cell array of flash memory device generating failure errors.
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公开(公告)号:US11977776B2
公开(公告)日:2024-05-07
申请号:US17679111
申请日:2022-02-24
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0613 , G06F3/0635 , G06F3/0679
Abstract: A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.
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公开(公告)号:US12159038B1
公开(公告)日:2024-12-03
申请号:US18203075
申请日:2023-05-30
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
Abstract: A flash memory controller of a storage device is coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit sends commands and data between the flash memory device and the processor The processor controls the I/O circuit to send a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array based on a smaller search range and to make the flash memory device determine whether the multiple page units are empty pages, the search range defined by a start page address stored in the flash memory device.
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公开(公告)号:US12105992B1
公开(公告)日:2024-10-01
申请号:US18202302
申请日:2023-05-26
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A method of a flash memory controller includes: using a processor to issue and generate a command signal into a control logic circuit though a bus; buffering the command signal in a specific queue of a specific channel controller of the I/O circuit; and using the arbitrator to control the specific buffer storing a first transmission history information of the specific communication interface.
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公开(公告)号:US12079483B2
公开(公告)日:2024-09-03
申请号:US17976901
申请日:2022-10-31
Applicant: Silicon Motion, Inc.
Inventor: Chia-Chi Liang , Hsiao-Chang Yen , Tsu-Han Lu
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0629 , G06F3/0679
Abstract: A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.
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公开(公告)号:US12073085B2
公开(公告)日:2024-08-27
申请号:US17852385
申请日:2022-06-29
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0655 , G06F3/0679
Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.
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公开(公告)号:US20230266921A1
公开(公告)日:2023-08-24
申请号:US17679111
申请日:2022-02-24
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0635 , G06F3/0613 , G06F3/0604 , G06F3/0679
Abstract: A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.
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公开(公告)号:US12164805B2
公开(公告)日:2024-12-10
申请号:US17679116
申请日:2022-02-24
Applicant: Silicon Motion, Inc.
Inventor: Tsu-Han Lu , Hsiao-Chang Yen
Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.
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