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公开(公告)号：US11843379B2
公开(公告)日：2023-12-12
申请号：US18092908
申请日：2023-01-03
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
CPC classification number: H03K21/026 , G06F1/3275 , H03K5/00006 , H03K21/10 , H03K21/406
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US10917119B2
公开(公告)日：2021-02-09
申请号：US16568221
申请日：2019-09-11
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
Abstract: A data storage system includes a processing circuit, a calculating circuit and an encoding circuit. The processing circuit receives a data byte from a host. The calculating circuit generates a cyclic redundancy check code according to an LBA, and combines the cyclic redundancy check code and the data byte into a data sector so that the data sector includes LBA-related information. The encoding circuit encodes the data sector to generate an error checking and correcting code, and combines the data sector and the error checking and correcting code into a storage data, so that the storage data includes the LBA-related information without including the LBA. Via the data sector and the storage data, the data storage system performs cyclic redundancy checking as well as error checking and correcting without storing the LBA for reducing 1-bit errors; and the LBA-related information does not include part or all of the LBA.
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公开(公告)号：US10409717B2
公开(公告)日：2019-09-10
申请号：US15853210
申请日：2017-12-22
Applicant: Silicon Motion, Inc.
Inventor： Sheng-I Hsu
Abstract: A data storage device includes a flash memory, a data processing module and a flash memory controller. Corresponding to the operation of a host, the flash memory controller arranges the flash memory to store data, and it stores a mapping table to record the mapping information between the flash memory and the logical address of the host. When the host transmits a trim command to invalidate a specific portion of the mapping table and the host manages to read the data of the specific portion, the flash memory controller sets up a flag to be open so that the data is transmitted to the host without the implement of the data processing module.
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公开(公告)号：US20180239670A1
公开(公告)日：2018-08-23
申请号：US15948586
申请日：2018-04-09
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Yang-Chih Shen , Sheng-I Hsu
Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.
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公开(公告)号：US20220224339A1
公开(公告)日：2022-07-14
申请号：US17707992
申请日：2022-03-30
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
IPC: H03K21/02 , H03K21/10 , G06F1/3234 , H03K5/00 , H03K21/40
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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Patent Agency Ranking
公开(公告)号：US20220094364A1
公开(公告)日：2022-03-24
申请号：US17331577
申请日：2021-05-26
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
IPC: H03K21/02 , H03K5/00 , H03K21/10 , H03K21/40 , G06F1/3234
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.
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公开(公告)号：US11050427B1
公开(公告)日：2021-06-29
申请号：US17029068
申请日：2020-09-23
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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8.发明申请公开(公告)号：US20200249873A1
公开(公告)日：2020-08-06
申请号：US16852526
申请日：2020-04-19
Applicant: Silicon Motion, Inc.
Inventor： Sheng-I Hsu , Ching-Chin Chang
Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.
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9.发明申请公开(公告)号：US20200159450A1
公开(公告)日：2020-05-21
申请号：US16271899
申请日：2019-02-11
Applicant: Silicon Motion Inc.
Inventor： Sheng-I Hsu , Ching-Chin Chang
Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.
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公开(公告)号：US20200153461A1
公开(公告)日：2020-05-14
申请号：US16745255
申请日：2020-01-16
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.
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