公开(公告)号：US20250068900A1

公开(公告)日：2025-02-27

申请号：US18386901

申请日：2023-11-03

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  ANDREW KUNIL CHOE ,  HOA VU

IPC: G06N3/065

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, a first set of columns storing W+ weights and a second set of columns storing W− weights; and an output circuit to receive a first current from a respective column in the first set of columns and a second current from a respective column in the second set of columns and to generate a first voltage and a second voltage, the output circuit comprising a first current-to-voltage converter comprising a first integration capacitor to provide the first voltage equal to an initial voltage minus a first discharge value due to the first current, and a second current-to-voltage converter comprising a second integration capacitor to provide the second voltage equal to the initial voltage minus a second discharge value due to the second current.