公开(公告)号：US20240338144A1

公开(公告)日：2024-10-10

申请号：US18212066

申请日：2023-06-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  HOA VU ,  STANLEY HONG ,  THUAN VU

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/062 ,  G06F3/0679 ,  G11C16/08

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

公开(公告)号：US20250068900A1

公开(公告)日：2025-02-27

申请号：US18386901

申请日：2023-11-03

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  ANDREW KUNIL CHOE ,  HOA VU

IPC: G06N3/065

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, a first set of columns storing W+ weights and a second set of columns storing W− weights; and an output circuit to receive a first current from a respective column in the first set of columns and a second current from a respective column in the second set of columns and to generate a first voltage and a second voltage, the output circuit comprising a first current-to-voltage converter comprising a first integration capacitor to provide the first voltage equal to an initial voltage minus a first discharge value due to the first current, and a second current-to-voltage converter comprising a second integration capacitor to provide the second voltage equal to the initial voltage minus a second discharge value due to the second current.

公开(公告)号：US20240282351A1

公开(公告)日：2024-08-22

申请号：US18195322

申请日：2023-05-09

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  HOA VU ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  DUC NGUYEN ,  HIEN PHAM

IPC: G11C7/16 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/16 ,  G11C7/12 ,  G11C7/14

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.