公开(公告)号：US09245638B2

公开(公告)日：2016-01-26

申请号：US14216776

申请日：2014-03-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域中的第一和第二区域，设置在所述沟道区域和所述冷杉区域上方的浮置栅极，设置在所述沟道区域上方且横向邻近 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

公开(公告)号：US20140198578A1

公开(公告)日：2014-07-17

申请号：US14216776

申请日：2014-03-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。