公开(公告)号：US20240339136A1

公开(公告)日：2024-10-10

申请号：US18206488

申请日：2023-06-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Kha Nguyen ,  Anh Ly ,  Hieu Van Tran ,  Hien Pham ,  Henry Tran

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/12

Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.