公开(公告)号：US12299562B2

公开(公告)日：2025-05-13

申请号：US17090481

申请日：2020-11-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Vipin Tiwari ,  Han Tran ,  Hien Pham

IPC: G06N3/063 ,  G06N3/065

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

公开(公告)号：US11087207B2

公开(公告)日：2021-08-10

申请号：US15991890

申请日：2018-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US20210035643A1

公开(公告)日：2021-02-04

申请号：US17075691

申请日：2020-10-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Kha Nguyen ,  Hien Pham ,  Stanley Hong ,  Stephen T. Trinh

IPC: G11C16/14 ,  H02M3/07 ,  G11C16/30

Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.

公开(公告)号：US20190205729A1

公开(公告)日：2019-07-04

申请号：US15936983

申请日：2018-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/04 ,  G11C16/04 ,  G06F17/16 ,  G06N3/063

CPC classification number: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C16/0425 ,  H03F3/45269

Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

公开(公告)号：US12279428B2

公开(公告)日：2025-04-15

申请号：US18520526

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

公开(公告)号：US12248870B2

公开(公告)日：2025-03-11

申请号：US18520500

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/04 ,  G06N3/065 ,  G11C11/54

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

公开(公告)号：US12062397B2

公开(公告)日：2024-08-13

申请号：US17585261

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Kha Nguyen ,  Hien Pham ,  Duc Nguyen

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

公开(公告)号：US11120881B2

公开(公告)日：2021-09-14

申请号：US17075691

申请日：2020-10-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Kha Nguyen ,  Hien Pham ,  Stanley Hong ,  Stephen T. Trinh

IPC: G11C5/14 ,  G11C16/14 ,  H02M3/07 ,  G11C16/30

Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.

公开(公告)号：US20200019849A1

公开(公告)日：2020-01-16

申请号：US16151259

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Thuan Vu ,  Anh Ly ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/063 ,  G06F3/06 ,  G06F11/16

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

公开(公告)号：US12237011B2

公开(公告)日：2025-02-25

申请号：US17853315

申请日：2022-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.