公开(公告)号：US20220130477A1

公开(公告)日：2022-04-28

申请号：US17571443

申请日：2022-01-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Guangming Lin ,  Xiaozhou Qian ,  Xiao Yan Pl ,  Vipin Tiwari ,  Zhenlin Ding

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10

Abstract: The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.