-
公开(公告)号：US11588490B2
公开(公告)日：2023-02-21
申请号：US17389663
申请日：2021-07-30
发明人： Jong Suk Lee , Young Bok Kim , Chung Hwan Son , Seok Jae Oh , Yeh Ju Ka
摘要： The present disclosure discloses a digital loop filter in an all-digital phase-locked loop. The digital loop filter may include a selection circuit configured to output one of a first data signal and a second data signal as valid data, a first operation circuit configured to output a first operation signal by adding or subtracting the valid data and a first register signal, a first register circuit configured to register the first operation signal and output the first operation signal as the first register signal, a second operation circuit configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and a second register circuit configured to store the second operation signal and output the second operation signal as a control signal.
-
公开(公告)号：US11509314B2
公开(公告)日：2022-11-22
申请号：US17389698
申请日：2021-07-30
发明人： Jong Suk Lee , Young Bok Kim , Chung Hwan Son , Seok Jae Oh , Yeh Ju Ka
摘要： The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.
-
公开(公告)号：US11641267B2
公开(公告)日：2023-05-02
申请号：US17443792
申请日：2021-07-27
发明人： Jong Suk Lee , Young Bok Kim , Chung Hwan Son , Seok Jae Oh , Soo Yeun Lee , Yeh Ju Ka
摘要： The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.
-
公开(公告)号：US11526136B2
公开(公告)日：2022-12-13
申请号：US17443799
申请日：2021-07-27
发明人： Jong Suk Lee , Young Bok Kim , Chung Hwan Son , Seok Jae Oh , Yeh Ju Ka
摘要： The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.
-
-
-
搜索结果
4 条记录 (耗时 0.016 秒)