公开(公告)号：US20190385945A1

公开(公告)日：2019-12-19

申请号：US16555890

申请日：2019-08-29

Applicant: Socionext Inc.

Inventor： Chika ITO ,  Isaya SOBUE

IPC: H01L23/528 ,  H01L27/04

Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.