公开(公告)号：US20240213300A1

公开(公告)日：2024-06-27

申请号：US18598870

申请日：2024-03-07

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hideyuki KOMURO

IPC: H01L27/092 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US20220415885A1

公开(公告)日：2022-12-29

申请号：US17902537

申请日：2022-09-02

Applicant: Socionext Inc.

Inventor： Isaya SOBUE

IPC: H01L27/07 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L23/528

Abstract: A layout structure of a capacitive element using forksheet FETs is provided. A capacitive structure constituting the capacitive element includes: a first transistor having a first nanosheet extending in the X direction and a first gate interconnect extending in the Y direction and surrounding the periphery of the first nanosheet; and a second transistor having a second nanosheet extending in the X direction and a second gate interconnect extending in the Y direction and surrounding the periphery of the second nanosheet. The face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and the face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.

公开(公告)号：US20210351202A1

公开(公告)日：2021-11-11

申请号：US17385451

申请日：2021-07-26

Applicant: SOCIONEXT INC.

Inventor： Isaya SOBUE

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.

公开(公告)号：US20220415882A1

公开(公告)日：2022-12-29

申请号：US17895785

申请日：2022-08-25

Applicant: SOCIONEXT INC

Inventor： Isaya SOBUE

IPC: H01L27/02

Abstract: In an IO region of a semiconductor integrated circuit device, placed is an IO cell row including a signal IO cell and a power IO cell supplying a first power supply. The power IO cell includes first and second external terminals connected to an external connection pad and an electrostatic discharge (ESD) protection device formed at least in a region between the first and second external terminals. The first external terminal is placed at a position having an overlap in the Y direction with a power supply line for a second power supply.

公开(公告)号：US20210184035A1

公开(公告)日：2021-06-17

申请号：US17187179

申请日：2021-02-26

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi TANAKA ,  Isaya SOBUE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L23/522 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate and a resistance element provided above the semiconductor substrate, the resistance element includes a conductive pattern using a gate electrode film formed simultaneously with a gate electrode film arranged on a side surface of a semiconductor nanowire of a VNW transistor, and there is fabricated the semiconductor device that includes the VNW transistor having the semiconductor nanowire and the resistance element having sufficient electrical resistance.

公开(公告)号：US20190385945A1

公开(公告)日：2019-12-19

申请号：US16555890

申请日：2019-08-29

Applicant: Socionext Inc.

Inventor： Chika ITO ,  Isaya SOBUE

IPC: H01L23/528 ,  H01L27/04

Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.

公开(公告)号：US20250072121A1

公开(公告)日：2025-02-27

申请号：US18946496

申请日：2024-11-13

Applicant: Socionext Inc.

Inventor： Isaya SOBUE

IPC: H01L27/02

Abstract: A first impurity region and a second impurity region, having first and second types of conductivity, respectively, are formed on a substrate, spaced apart from each other in a first direction, in contact with a third impurity region a fourth impurity region, which are also provided on the substrate with the second and first types of conductivity, respectively. Interconnects that extend in a second direction, which is different from the first direction, are formed in the substrate, on the side of the third impurity region facing the fourth impurity region side, and on the side of the fourth impurity region facing the third impurity region. By this means, when multiple diodes are arranged next to each other, it is still possible to prevent or substantially prevent the semiconductor device's chip size from increasing.

公开(公告)号：US20220102479A1

公开(公告)日：2022-03-31

申请号：US17546463

申请日：2021-12-09

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hideyuki KOMURO

IPC: H01L49/02 ,  H01L27/06

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US20210366902A1

公开(公告)日：2021-11-25

申请号：US17394065

申请日：2021-08-04

Applicant: SOCIONEXT INC.

Inventor： Isaya SOBUE

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A layout structure of a capacitive element using a complementary FET (CFET) and having a high breakdown voltage is provided. In the capacitive element, first and second transistors overlap as viewed in plan, and the gates thereof are mutually connected. Third and fourth transistors overlap as viewed in plan, and the gates thereof are mutually connected. Nodes of the first and third transistors are mutually connected through a local interconnect, and nodes of the second and fourth transistors are mutually connected through a local interconnect.

公开(公告)号：US20200083252A1

公开(公告)日：2020-03-12

申请号：US16684322

申请日：2019-11-14

Applicant: SOCIONEXT INC.

Inventor： Isaya SOBUE

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.