公开(公告)号：US20250006735A1

公开(公告)日：2025-01-02

申请号：US18882304

申请日：2024-09-11

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Tomoya TSURUTA ,  Yasuhiro NAKAOKA

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/118

Abstract: A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

公开(公告)号：US20220246644A1

公开(公告)日：2022-08-04

申请号：US17720802

申请日：2022-04-14

Applicant: Socionext Inc.

Inventor： Yasuhiro NAKAOKA

IPC: H01L27/118 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively.

公开(公告)号：US20210375863A1

公开(公告)日：2021-12-02

申请号：US17404639

申请日：2021-08-17

Applicant: SOCIONEXT INC.

Inventor： Hideyuki KOMURO ,  Tomoya TSURUTA ,  Yasuhiro NAKAOKA

IPC: H01L27/092 ,  H01L27/06 ,  H01L27/118 ,  H01L27/02 ,  H01L21/8238

Abstract: A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.