公开(公告)号：US12048134B2

公开(公告)日：2024-07-23

申请号：US17879415

申请日：2022-08-02

Applicant: Socionext Inc.

Inventor： Masanobu Hirose ,  Yasunori Murase

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H10B10/18

Abstract: Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.