公开(公告)号：US20060184603A1

公开(公告)日：2006-08-17

申请号：US11056036

申请日：2005-02-11

申请人： Son Trong ,  Mark Erle ,  Bruce Fleischer ,  Juergen Haess ,  Michael Kelly ,  Klaus Kroener ,  Martin Schmookler ,  Eric Schwarz

发明人： Son Trong ,  Mark Erle ,  Bruce Fleischer ,  Juergen Haess ,  Michael Kelly ,  Klaus Kroener ,  Martin Schmookler ,  Eric Schwarz

IPC分类号： G06F7/52

CPC分类号： G06F7/53 ,  G06F7/74

摘要： The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to prior art decreases the calculation speed in the multiplier. In order to provide a method and respective electronic circuit, wherein the zero detection is earlier completed, it is proposed to use a leading zero anticipation (LZA) hardware—i.e., an LZA circuit (40), which exists usually anyway in floating point processor adders for calculating the number of leading zeros for operand normalization purposes—for performing a zero detection of the product by aid of the partial results (16, 17) emerging at the output of the Wallace tree of the multiplier. MSB-most and LSB-most margin bits (24, 26) of the partial (16, 17) results which cannot be processed by the LZA circuit (40), are read directly from the final product bit string (22).

摘要翻译： 本发明涉及一种用于在计算机处理器的运算单元中执行乘法运算的方法和电路。 在其乘数中，为了适当地设置条件代码和溢出状态信息，需要对所得到的产品位串（22）进行零检测。 根据现有技术的零检测降低了乘法器中的计算速度。 为了提供一种方法和各自的电子电路，其中零检测较早完成，提出使用前导零预期（LZA）硬件即LZA电路（40），其通常在浮点处理器 用于计算操作数归一化目的的前导零数量的加法器，用于通过在乘法器的华莱士树的输出处出现的部分结果（16,17）执行零检测。 从最终产品位串（22）直接读取不能由LZA电路（40）处理的部分（16,17）结果的MSB最大和LSB最大的边缘位（24,26）。

公开(公告)号：US20060173946A1

公开(公告)日：2006-08-03

申请号：US11341256

申请日：2006-01-26

申请人： Son Trong ,  Juergen Haess ,  Klaus Kroener ,  Eric Schwarz

发明人： Son Trong ,  Juergen Haess ,  Klaus Kroener ,  Eric Schwarz

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F2207/3812

摘要： A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC−expB+CV).

摘要翻译： 一种用于执行二进制模式和十六进制模式的方法和系统根据公式A * C + B在浮点算术单元中乘法 - 浮点运算，其中A，B和C操作数各自具有分数和指数部分expA ，expB和expC和乘积A * C的指数被计算，并且与包含专用于使用无符号偏移指数的指数偏差值的加数指数进行比较，其中比较产生用于将加数与 产品操作数，其中移位量计算根据公式（expA + expC-expB + CV）为二进制和十六进制提供公共值CV。

公开(公告)号：US20060179097A1

公开(公告)日：2006-08-10

申请号：US11054110

申请日：2005-02-09

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。 该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US20060179096A1

公开(公告)日：2006-08-10

申请号：US11055232

申请日：2005-02-10

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/49947 ,  G06F7/5443

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US20060179100A1

公开(公告)日：2006-08-10

申请号：US11054686

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Lawrence Powell ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Lawrence Powell ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

IPC分类号： G06F7/38

CPC分类号： G06F9/3826 ,  G06F9/30014 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3885

摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.

摘要翻译： 一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。 该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。 该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。 这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在 存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。 此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作 在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

公开(公告)号：US20060179286A1

公开(公告)日：2006-08-10

申请号：US11054201

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

IPC分类号： G06F9/44

CPC分类号： G06F9/3867 ,  G06F9/3838

摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.

摘要翻译： 用于执行浮点负载有限次序执行的系统。 该系统包括构成管道的多个阶段，这些阶段包括早期阶段。 该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。 该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。 确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。 与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。 如果结果地址等于加载地址，则会发生WAW条件。 响应于发生的WAW状态，写入算术指令的结果被抑制。

公开(公告)号：US20060047738A1

公开(公告)日：2006-03-02

申请号：US10930129

申请日：2004-08-31

申请人： Eric Schwarz ,  Martin Schmookler

发明人： Eric Schwarz ,  Martin Schmookler

IPC分类号： G06F7/38

CPC分类号： G06F7/49947 ,  G06F7/491 ,  G06F7/49963

摘要： A method of processing data employs a new rounding mode called “round for reround” on the original arithmetic instruction in the hardware precision, and then 2) invoking an instruction which specifies a variable rounding precision and possibly explicitly sets the rounding mode which we have called the ReRound instruction. The precise result of the arithmetic operation is first truncated to the hardware format precision “p”, forming an intermediate result. If only zeros are dropped during truncation, then the intermediate result is equal to the precise result, and this result is said to be “exact”, otherwise, it is “inexact”. When the intermediate result is inexact and its least significant digit is either zero or five, then that digit is incremented to one or six respectively forming the rounded result. Thus, when the least significant digit of a rounded result is zero or five the result could be construed to be exact or exactly halfway between two machine representations if it were later rounded to one less digit of precision. For all other values, it is obvious that the result is inexact and not halfway between two machine representations for later roundings to fewer than “p” digits of precision. A nice mathematical property of this rounding mode is that results stay ordered and in a hardware implementation it is guaranteed that the incrementation of the least significant digit does not cause a carry into the next digit of the result.

摘要翻译： 处理数据的方法采用在硬件精度上对原始算术指令称为“round for reround”的新的舍入模式，然后2）调用指定变量舍入精度的指令，并可能明确地设置我们称之为舍入模式 ReRound指令。 算术运算的精确结果首先被截断为硬件格式精度“p”，形成中间结果。 如果在截断期间仅删除零，则中间结果等于精确结果，并且该结果被称为“精确”，否则为“不精确”。 当中间结果不精确，其最低有效位为零或五时，则该数字分别增加到一个或六个，分别形成舍入结果。 因此，当舍入结果的最低有效数字为零或五时，如果结果被稍后舍入为一个较小的精度数字，则结果可以被解释为两个机器表示之间的精确或准确的中间。 对于所有其他值，很明显，结果是不精确的，而不是两个机器表示之间的中间，以便稍后的舍入少于“p”位精度。 这种舍入模式的一个很好的数学属性是结果保持有序，并且在硬件实现中，保证最低有效位的递增不会导致结果的下一个数字的进位。

公开(公告)号：US20060179090A1

公开(公告)日：2006-08-10

申请号：US11054232

申请日：2005-02-09

申请人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/00

CPC分类号： H03M7/12

摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.

摘要翻译： 一种从二进制转换为十进制的方法。 该方法包括接收二进制数，该二进制数包括一个或多个位组。 累积和设为零。 累加和是二进制编码十进制（BCD）格式。 从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换 成为5,1代码格式，产生临时总和。 循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。 循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。 一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

公开(公告)号：US20060179091A1

公开(公告)日：2006-08-10

申请号：US11054233

申请日：2005-02-09

申请人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/00

CPC分类号： H03M7/12

摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.

摘要翻译： 一种从二进制转换为十进制的方法。 该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。 运行总和和运行进位设置为零。 对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。 步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。 在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。

公开(公告)号：US20060179098A1

公开(公告)日：2006-08-10

申请号：US11054234

申请日：2005-02-09

申请人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

发明人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

IPC分类号： G06F7/38

CPC分类号： G06F7/74 ,  G06F7/491 ,  G06F2207/4911

摘要： A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least one leading zero digit and set to one otherwise. The method also includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least two leading zero digits. A group two switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least two leading zero digits and set to one otherwise. The method further includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains three leading zero digits. A group three switch is set to zero if was determined that the BCD number represented by the DPD encoded data contains three leading zero digits and set to one otherwise.

摘要翻译： 一种引导零检测的方法。 如果由DPD编码数据表示的BCD数字包含至少一个前导零数字，则该方法包括接收表示三位BCD号码的DPD编码数据，并直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少一个前导零数字并且另外设置为一个，则将一组开关设置为零。 如果由DPD编码数据表示的BCD数字包含至少两个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少两个前导零数字并且另外设置为一个，则组二开关被设置为零。 如果由DPD编码数据表示的BCD数字包含三个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含三个前导零数字并且另外设置为一个，则组三开关被设置为零。