公开(公告)号：US20090327649A1

公开(公告)日：2009-12-31

申请号：US12495375

申请日：2009-06-30

申请人： Soumya BANERJEE ,  Michael Gottlieb Jensen ,  Ryan C. Kinter

发明人： Soumya BANERJEE ,  Michael Gottlieb Jensen ,  Ryan C. Kinter

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

摘要翻译： 提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。 宏TLB缓存所有线程的内存页面的地址转换信息。 微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。 用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。 纳米TLB还包括替换信息以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。 根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。

公开(公告)号：US20120221838A1

公开(公告)日：2012-08-30

申请号：US13404350

申请日：2012-02-24

申请人： Soumya BANERJEE ,  Gideon D. INTRATER ,  Michael Gottlieb JENSEN

发明人： Soumya BANERJEE ,  Gideon D. INTRATER ,  Michael Gottlieb JENSEN

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F11/2236

摘要： The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.

摘要翻译： 本发明提供了用于检测处理器中的错误原因的软件可编程硬件状态机，并防止发生错误。 提供了一种处理器核心，其包括执行单元，可编程屏蔽寄存器和存储表示分配给执行单元的指令的值的缓冲器。 处理器核心还包括控制逻辑以确定掩模寄存器中的序列与缓冲器中的序列之间是否存在匹配，并且在检测到匹配时，产生控制信号以执行期望的动作。 期望的操作防止对处理器的架构状态发生不期望的改变。 处理器核心还包括可编程定位寄存器。 在一个实施例中，控制逻辑基于存储在定位寄存器中的控制位产生控制信号。

公开(公告)号：US20090080651A1

公开(公告)日：2009-03-26

申请号：US11862154

申请日：2007-09-26

申请人： Soumya BANERJEE ,  Paritosh KULKARNI

发明人： Soumya BANERJEE ,  Paritosh KULKARNI

IPC分类号： G06F12/14 ,  H04L9/00

CPC分类号： G06F12/14 ,  G06F21/12 ,  G06F21/71

摘要： A computer readable medium includes executable instructions to describe an intellectual property core with a key check mechanism configured to compare an external key with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.

摘要翻译： 计算机可读介质包括可执行指令，用于使用配置为响应于指定事件将外部密钥与内部密钥进行比较的密钥检查机制来描述知识产权核心。 响应于外部键和内部键之间的匹配执行待命指令。 响应于外部键和内部键之间的不匹配而执行意外的动作。