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1.发明授权Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor 有权多线程微处理器中的三层翻译后备缓冲层次结构公开(公告)号：US07925859B2
公开(公告)日：2011-04-12
申请号：US12495375
申请日：2009-06-30
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
摘要翻译： 提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。 宏TLB缓存所有线程的内存页面的地址转换信息。 微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。 用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。 纳米TLB还包括替换信息以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。 根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。
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2.发明授权Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor 有权多线程微处理器中的三层翻译后备缓冲层次结构公开(公告)号：US07558939B2
公开(公告)日：2009-07-07
申请号：US11075041
申请日：2005-03-08
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
摘要翻译： 提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。 宏TLB缓存所有线程的内存页面的地址转换信息。 微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。 用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。 纳米TLB还包括替换信息，以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。 根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。
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3.发明申请Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor 有权多线程微处理器中的三层翻译后备缓冲层次结构公开(公告)号：US20090327649A1
公开(公告)日：2009-12-31
申请号：US12495375
申请日：2009-06-30
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
摘要翻译： 提供了同时执行多个指令线程的多线程处理器中的三层TLB架构。 宏TLB缓存所有线程的内存页面的地址转换信息。 微型TLB缓存缓存在宏TLB中的存储器页面的子集的翻译信息。 用于每个线程的相应的nano-TLB仅缓存针对相应线程的转换信息。 纳米TLB还包括替换信息以指示nano-TLB / micro-TLB中的哪些条目最近使用相应线程的翻译信息。 根据替换信息，如果从微型TLB迁移，最近使用的信息被复制到nano-TLB。
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4.发明授权Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency 有权具有优化线程调度器的多线程微处理器，可提高管道利用效率公开(公告)号：US08151268B2
公开(公告)日：2012-04-03
申请号：US12684564
申请日：2010-01-08
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/30087 , G06F9/3009 , G06F9/3867
摘要： A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.
摘要翻译： 提供了用于同时执行多个线程的多线程处理器。 该处理器包括一个执行流水线和一个线程调度器，它将线程的指令分派到执行流水线。 执行流水线被配置为当线程上下文的一个或多个指令在执行流水线中停止时，生成与线程上下文相关联的线程上下文（TC）刷新指示符。 与线程上下文冲洗信号相关联的线程上下文中的一个或多个指令可被刷新或无效。
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公开(公告)号：US07681014B2
公开(公告)日：2010-03-16
申请号：US11191258
申请日：2005-07-27
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3885 , G06F9/4881
摘要： An instruction dispatching apparatus in a multi threading microprocessor that concurrently executes N threads each in one of G groups each having one of P priorities. G round-robin vectors each have N bits corresponding to the threads, each being a 1-bit left-rotated and subsequently sign-extended version of an N-bit vector with a single bit true of the last thread selected for dispatching in the group. Each of N G-input muxes receive a corresponding one of the N bits of each of the round-robin vectors and selects for output one of the inputs specified by the corresponding thread's group. Selection logic selects for dispatching one of the N instructions corresponding to the thread whose dispatch value is greater than or equal to any of the N threads left thereof. Each dispatch value comprises a least-significant bit of the corresponding mux output, a most-significant dispatchable instruction bit, and middle thread group priority bits.
摘要翻译： 一种多线程微处理器中的指令调度装置，其并行地执行每个具有P个优先级之一的G组之一的N个线程。 G循环向量各自具有对应于线程的N比特，每个N个比特是1比特的左旋转和随后的符号扩展版本的N比特向量，其中所选择的最后一个线程的单个比特为真，用于在该组中进行分派 。 N个G输入多路复用器中的每一个接收每个循环向量的N个比特中的相应一个，并且选择用于输出由相应线程组指定的输入中的一个。 选择逻辑选择用于调度对应于其调度值大于或等于其剩余的N个线程中的任何一个的线程的N个指令中的一个指令。 每个调度值包括对应的多路复用器输出的最低有效位，最重要的可调度指令位和中间线程组优先级位。
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6.发明申请MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY 有权具有优化螺纹调度器的多功能微处理器，用于提高管道利用效率公开(公告)号：US20100115244A1
公开(公告)日：2010-05-06
申请号：US12684564
申请日：2010-01-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/30087 , G06F9/3009 , G06F9/3867
摘要： A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.
摘要翻译： 提供了用于同时执行多个线程的多线程处理器。 该处理器包括一个执行流水线和一个线程调度器，它将线程的指令分派到执行流水线。 执行流水线被配置为当线程上下文的一个或多个指令在执行流水线中停止时，生成与线程上下文相关联的线程上下文（TC）刷新指示符。 与线程上下文冲洗信号相关联的线程上下文中的一个或多个指令可被刷新或无效。
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公开(公告)号：US07660969B2
公开(公告)日：2010-02-09
申请号：US11620362
申请日：2007-01-05
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3885 , G06F9/4881
摘要： A concurrent instruction dispatch apparatus includes a group indicator for each of a plurality of threads that indicates which one of a plurality of groups of the threads the thread belongs to. A group priority indicator for each group indicates an instruction dispatch priority relative to the other groups. Selection logic selects a thread for dispatching an instruction thereof based on the group and group priority indicators. A bifurcated scheduler includes first scheduler logic that issues instructions of the threads to an execution unit, second scheduler logic that enforces a thread scheduling policy, and an interface. A group indicator indicates which group each thread belongs to, a priority for each group, and execution information for each thread. The first scheduler logic issues the instructions based on the group priorities and group indicators, and the second scheduler logic updates the group indicators based on the instruction execution information.
摘要翻译： 并行指令调度装置包括指示线程所属的多个线程组中的哪一组的多个线程中的每一个的组指示符。 每个组的组优先级指示符指示相对于其他组的指令调度优先级。 选择逻辑基于组和组优先级指示器选择用于调度其指令的线程。 分叉调度器包括将线程的指令发布到执行单元的第一调度器逻辑，强制执行线程调度策略的第二调度器逻辑和接口。 组指示符指示每个线程所属的组，每个组的优先级以及每个线程的执行信息。 第一调度器逻辑基于组优先级和组指示器发出指令，并且第二调度器逻辑基于指令执行信息更新组指示符。
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8.发明授权Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages 有权优先级线程选择部分基于在流水线阶段提供指令操作数寄存器使用的状态信息的失速可能性公开(公告)号：US07664936B2
公开(公告)日：2010-02-16
申请号：US11051998
申请日：2005-02-04
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/382 , G06F9/3838 , G06F9/3861
摘要： An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.
摘要翻译： 提供了一种用于在多线程处理器中同时执行的多个线程之间调度指令调度的装置。 该装置包括：指令解码器，用于生成来自每个线程的指令的寄存器使用信息;基于寄存器使用信息和当前在执行流水线中执行的指令的状态信息生成每个指令的优先级的优先级生成器，以及选择 基于指令的优先级从至少一个线程调度至少一条指令的逻辑。 优先级表示指令在执行流水线中执行的可能性，而不会停顿。 例如，如果指令很少或没有寄存器依赖性或其数据已知可用，则指令可能具有高优先级; 或者如果具有强的寄存器依赖性或者不可缓存或同步的存储空间加载指令，则可能具有低优先级。
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9.发明授权Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency 有权具有优化线程调度器的多线程微处理器，可提高管道利用效率公开(公告)号：US07657891B2
公开(公告)日：2010-02-02
申请号：US11051979
申请日：2005-02-04
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/30087 , G06F9/3009 , G06F9/3867
摘要： A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.
摘要翻译： 提供了用于同时执行多个线程的多线程处理器。 该处理器包括一个执行流水线和一个线程调度器，它将线程的指令分派到执行流水线。 执行流水线检测由分派指令引起的停顿事件，并刷新执行流水线以使其他线程的指令能够继续执行。 执行流水线与调度程序进行通信，该线程引起停止事件，并且调度器停止线程的调度指令，直到停止条件终止。 在一个实施例中，执行流水线仅刷新包括引起事件的指令的线程。 在一个实施例中，如果线程是唯一的可运行线程，则执行流水线停止而不是刷新。 在一个实施例中，处理器包括滑动缓冲器，刷新的指令被回滚到所述缓冲器缓冲器，使得指令提取流水线不需要被刷新，仅仅是执行流水线。
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10.发明授权公开(公告)号：US07707389B2
公开(公告)日：2010-04-27
申请号：US10698061
申请日：2003-10-31
申请人： Soumya Banerjee , John L. Kelley , Ryan C. Kinter
发明人： Soumya Banerjee , John L. Kelley , Ryan C. Kinter
IPC分类号： G06F9/30
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/30174 , G06F9/30178
摘要： A method and apparatus for recoding one or more instruction sets. An expand instruction and an expandable instruction are read from an instruction cache. A tag compare and way selection unit checks to verify each instruction is a desired instruction. An instruction staging unit dispatches the expand instruction to a first recoder and the expandable instruction to a second recoder of a recoding unit. At least one information bit based on the expand instruction is generated at the first recoder. The second recoder uses the at least one information bit generated at the first recoder to recode the expandable instruction, and the recoded expandable instruction is placed in an instruction buffer.
摘要翻译： 一种用于重新编码一个或多个指令集的方法和装置。 从指令高速缓存中读取扩展指令和可扩展指令。 标签比较和方式选择单元检查以验证每条指令是否是所需的指令。 指令分段单元将扩展指令分派到第一重新编码器，并将扩展指令分配给编码单元的第二编码器。 在第一记录器处产生基于扩展指令的至少一个信息位。 第二记录器使用在第一记录器处生成的至少一个信息位对可扩展指令进行重新编码，并且重新编码的可扩展指令被放置在指令缓冲器中。
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