公开(公告)号：US5307285A

公开(公告)日：1994-04-26

申请号：US949745

申请日：1992-09-23

申请人： Steffen Storandt ,  Ralf-Johannes Lenninger

发明人： Steffen Storandt ,  Ralf-Johannes Lenninger

IPC分类号： G06F11/28 ,  G06F11/22 ,  G06F15/78 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F15/7832

摘要： A circuit configuration for emulating a microcontroller includes connection terminals being pin-compatible with the microcontroller to be emulated. A bond-out chip of the microcontroller is connected to the connection terminals. A reprogrammable memory device is provided. A logic configuration provides direct access from at least some of the connection terminals to the reprogrammable memory device. The circuit configuration has a three-dimensional measurement being at least approximately identical to the three-dimensional measurement of the microcontroller to be emulated.

摘要翻译： 用于仿真微控制器的电路配置包括与待仿真的微控制器引脚兼容的连接端子。 微控制器的熔接芯片连接到连接端子。 提供可编程存储器件。 逻辑配置提供从至少一些连接终端到可再编程存储器设备的直接访问。 电路配置具有至少大致相同于待仿真的微控制器的三维测量的三维测量。

公开(公告)号：US5138640A

公开(公告)日：1992-08-11

申请号：US611018

申请日：1990-11-09

申请人： Rod Fleck ,  Karl-Heinz Mattheis ,  Christoph Meinhold ,  Steffen Storandt

发明人： Rod Fleck ,  Karl-Heinz Mattheis ,  Christoph Meinhold ,  Steffen Storandt

IPC分类号： G04F10/04 ,  G01P3/489 ,  H03K5/00

CPC分类号： G01P3/489

摘要： A circuit configuration for improving the resolution of successive pulsed signals over time includes first and second counters each having one clock input, the clock input of the first counter being supplied with a first clock signal, and the clock input of the second counter being supplied with a second clock signal having a n-multiple frequency of the first clock signal. The first counter has a control input and a counter output, the control input of the first counter being supplied with successive pulsed signals. The second counter has a counter input, an overflow output and a write input, the write input of the second counter being connected to the overflow output of the second counter. A register has a data input, a data output, and a write input, the data input of the register being connected to the counter output of the first counter, the write input of the register being connected to the control input of the first counter, and the data output of the register being connected to the counter input of the second counter. The counter state of the first counter is written into the register through the counter output of the first counter and the first counter is subsequently reset, upon one of the successive pulsed signals being supplied to the control input of the first counter. The second counter assumes the value of the register when an overflow signal is tripped.

摘要翻译： 用于随时间提高连续脉冲信号的分辨率的电路配置包括第一和第二计数器，每个具有一个时钟输入，第一计数器的时钟输入被提供有第一时钟信号，并且第二计数器的时钟输入被提供 具有第一时钟信号的n倍频率的第二时钟信号。 第一计数器具有控制输入和计数器输出，第一计数器的控制输入被提供有连续的脉冲信号。 第二计数器具有计数器输入，溢出输出和写入输入，第二计数器的写入输入连接到第二计数器的溢出输出。 寄存器具有数据输入，数据输出和写入输入，寄存器的数据输入连接到第一计数器的计数器输出，寄存器的写入输入连接到第一计数器的控制输入， 并且寄存器的数据输出连接到第二计数器的计数器输入端。 第一计数器的计数器状态通过第一计数器的计数器输出被写入寄存器，并且随后将连续的脉冲信号中的一个提供给第一计数器的控制输入而复位第一计数器。 当溢出信号跳闸时，第二个计数器取值为寄存器的值。