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1.发明申请ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A RECESS PRIOR TO THE WELL IMPLANTATION 有权通过在较好的植入前形成一个通道，提高通道半导体合金的沉积均匀性公开(公告)号：US20110156172A1
公开(公告)日：2011-06-30
申请号：US12908053
申请日：2010-10-20
申请人： Stephan Kronholz , Maciej Wiatr , Roman Boschke , Peter Javorka
发明人： Stephan Kronholz , Maciej Wiatr , Roman Boschke , Peter Javorka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L27/1203 , H01L29/1054 , H01L29/517 , H01L29/66651
摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。
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2.发明授权Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth 有权包括通过外延生长形成的Si / Ge半导体材料的PFET晶体管中的缺陷率的降低公开(公告)号：US08939765B2
公开(公告)日：2015-01-27
申请号：US12965118
申请日：2010-12-10
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7843 , H01L29/7848
摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。
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3.发明申请STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE 有权通过在门电极顶部的拐角环绕包含嵌入式应变诱导半导体合金的晶体管中的应变增强公开(公告)号：US20110101469A1
公开(公告)日：2011-05-05
申请号：US12893808
申请日：2010-09-29
申请人： Stephan Kronholz , Roman Boschke , Maciej Wiatr , Peter Javorka
发明人： Stephan Kronholz , Roman Boschke , Maciej Wiatr , Peter Javorka
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/26586 , H01L21/28052 , H01L21/28114 , H01L21/823807 , H01L21/82385 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
摘要翻译： 在MOS晶体管元件中，通过施加减小的宽度的间隔结构，应变诱导半导体合金可以嵌入在有源区中，并且与沟道区的偏移减小。 为了降低在栅极电极结构的顶部区域产生半导体残留物的可能性，可以引入半导体材料的一定程度的角圆化，这可以在外延生长应变诱导半导体之前通过离子注入来实现 材料。 这个概念可以有利地结合提供在早期制造阶段中提供的复杂的高k金属栅电极。
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4.发明授权Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode 有权晶体管中的应变增强，包括通过在栅电极的顶部进行角圆化的嵌入式应变诱导半导体合金公开(公告)号：US08338892B2
公开(公告)日：2012-12-25
申请号：US12893808
申请日：2010-09-29
申请人： Stephan Kronholz , Roman Boschke , Maciej Wiatr , Peter Javorka
发明人： Stephan Kronholz , Roman Boschke , Maciej Wiatr , Peter Javorka
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/26586 , H01L21/28052 , H01L21/28114 , H01L21/823807 , H01L21/82385 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
摘要翻译： 在MOS晶体管元件中，通过施加减小的宽度的间隔结构，应变诱导半导体合金可以嵌入在有源区中，并且与沟道区的偏移减小。 为了降低在栅极电极结构的顶部区域产生半导体残留物的可能性，可以引入半导体材料的一定程度的角圆化，这可以在外延生长应变诱导半导体之前通过离子注入来实现 材料。 这个概念可以有利地结合提供在早期制造阶段中提供的复杂的高k金属栅电极。
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5.发明授权Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation 有权通过在阱注入之前形成凹槽来提高通道半导体合金的沉积均匀性公开(公告)号：US08722486B2
公开(公告)日：2014-05-13
申请号：US12908053
申请日：2010-10-20
申请人： Stephan Kronholz , Maciej Wiatr , Roman Boschke , Peter Javorka
发明人： Stephan Kronholz , Maciej Wiatr , Roman Boschke , Peter Javorka
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L27/1203 , H01L29/1054 , H01L29/517 , H01L29/66651
摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。
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6.发明申请Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth 有权降低包含由外延生长形成的Si / Ge半导体材料的PFET晶体管的缺陷率公开(公告)号：US20110291163A1
公开(公告)日：2011-12-01
申请号：US12965118
申请日：2010-12-10
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7843 , H01L29/7848
摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。
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7.发明授权Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices 有权在密集封装的半导体器件中，在沟槽隔离结构中埋设蚀刻停止层以获得出色的表面平面度公开(公告)号：US08334573B2
公开(公告)日：2012-12-18
申请号：US12858727
申请日：2010-08-18
申请人： Maciej Wiatr , Markus Forsberg , Stephan Kronholz , Roman Boschke
发明人： Maciej Wiatr , Markus Forsberg , Stephan Kronholz , Roman Boschke
IPC分类号： H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.
摘要翻译： 先进的半导体器件中的沟槽隔离结构的材料侵蚀可以通过在早期制造阶段中合并适当的掩模层堆叠来减少。 例如，氮化硅材料可以在用于图案化有源区域并在其中形成应变诱导半导体合金的序列之前作为掩埋蚀刻停止层引入，其中特别地，在选择性外延生长工艺之前的相应的清洁工艺 已经被确定为在沉积层间介电材料时引起沉积相关不规则的主要来源。
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8.发明授权Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material 有权半导体元件形成在晶体衬底材料中并且包括嵌入式原位掺杂的半导体材料公开(公告)号：US08664049B2
公开(公告)日：2014-03-04
申请号：US12776879
申请日：2010-05-10
CPC分类号： H01L27/1207 , H01L21/823418 , H01L27/0629 , H01L29/66636 , H01L29/78 , H01L29/7845 , H01L29/7848
摘要： The PN junction of a substrate diode in a sophisticated SOI device may be formed on the basis of an embedded in situ doped semiconductor material, thereby providing superior diode characteristics. For example, a silicon/germanium semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material.
摘要翻译： 可以在嵌入式原位掺杂半导体材料的基础上形成复杂SOI器件中的衬底二极管的PN结，从而提供优异的二极管特性。 例如，可以在衬底材料的空腔中形成硅/锗半导体材料，其中可以选择空腔的尺寸和形状以避免与金属硅化物材料的过度相互作用。
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9.发明申请BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES 有权用于密封包装半导体器件中的超级表面平面的TRENCH隔离结构中的BURIED ETCH STOP LAY公开(公告)号：US20110049637A1
公开(公告)日：2011-03-03
申请号：US12858727
申请日：2010-08-18
申请人： Maciej Wiatr , Markus Forsberg , Stephan Kronholz , Roman Boschke
发明人： Maciej Wiatr , Markus Forsberg , Stephan Kronholz , Roman Boschke
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/28123 , H01L21/76224 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.
摘要翻译： 先进的半导体器件中的沟槽隔离结构的材料侵蚀可以通过在早期制造阶段中合并适当的掩模层堆叠来减少。 例如，氮化硅材料可以在用于图案化有源区域并在其中形成应变诱导半导体合金的序列之前作为掩埋蚀刻停止层引入，其中特别地，在选择性外延生长工艺之前的相应的清洁工艺 已经被确定为在沉积层间介电材料时引起沉积相关不规则的主要来源。
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10.发明申请SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU N-DOPED SEMICONDUCTOR MATERIAL 审中-公开在晶体衬底材料中形成的半导体元素和包含在N掺杂的半导体材料中的嵌入元件公开(公告)号：US20100327358A1
公开(公告)日：2010-12-30
申请号：US12822475
申请日：2010-06-24
CPC分类号： H01L27/1207
摘要： The PN junction of a substrate diode in a sophisticated semiconductor device may be formed on the basis of an embedded in situ N-doped semiconductor material thereby providing superior diode characteristics. For example, a silicon/carbon semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material.
摘要翻译： 可以在嵌入式原位N掺杂半导体材料的基础上形成复杂半导体器件中的衬底二极管的PN结，从而提供优异的二极管特性。 例如，可以在衬底材料的空腔中形成硅/碳半导体材料，其中可以选择空腔的尺寸和形状以避免与金属硅化物材料的过度相互作用。
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