Signal delaying device and method for dynamic delaying of a digitally sampled signal
    1.
    发明授权
    Signal delaying device and method for dynamic delaying of a digitally sampled signal 失效
    用于动态延迟数字采样信号的信号延迟装置和方法

    公开(公告)号:US07359469B2

    公开(公告)日:2008-04-15

    申请号:US10761136

    申请日:2004-01-20

    CPC classification number: H03H17/0275 H03H17/0027 H03K5/13

    Abstract: A signal delaying device (1) for the dynamic delaying of a digitally sampled input signal comprises a memory element (2) and a series-connected interpolation element (3). According to the invention, a register (30), which can be connected to the output side of the interpolation element (3), is arranged in parallel to the memory element (2) for intermediate storage of at least one sampled value (Sin(k)) of the input signal.

    Abstract translation: 用于动态延迟数字采样输入信号的信号延迟装置(1)包括存储元件(2)和串联连接的插值元件(3)。 根据本发明,可以连接到插值元件(3)的输出侧的寄存器(30)被布置成与存储元件(2)并联,用于中间存储至少一个采样值(S < SUB(k))的输入信号。

Patent Agency Ranking