公开(公告)号：US06282195B1

公开(公告)日：2001-08-28

申请号：US08780785

申请日：1997-01-09

申请人： Steven C. Miller ,  James E. Tornes

发明人： Steven C. Miller ,  James E. Tornes

IPC分类号： H04L1256

CPC分类号： H04L49/253 ,  H04L49/30

摘要： A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet. In addition, there may be bits within a packet used to indicate a coherent transaction, guarantee bandwidth, an error during transmission, or a sync barrier for write ordering. Other types of packets may include a fetch and operation packet with increment by one, a fetch and operation packet with decrement by one, a fetch and operation packet with clear, a store and operation packet with increment by one, a store and operation packet with decrement by one, a store and operation packet with a logical OR, and a store and operation packet with a logical AND.

摘要翻译： 一种用于在耦合到所述交换路由器的多个设备之间并发地发送分组化数据的交换路由器。 这些设备耦合到交换路由器的I / O端口。 然后将交换路由器编程为将数据包从各种源端口路由到多个目的端口。 可以通过交换路由器同时发送不同的分组。 分组由包含对应于分组路由，数据格式，大小和事务标识的信息的命令字组成。 此外，命令字可以包括用于将分组路由到目的地设备的目的地标识号，目的地设备用于发送回应用的源标识号，用于标记需要响应的请求的事务号，以及分组类型值 指示特定类型的数据包。 此外，在用于指示相干事务，保证带宽，传输期间的错误或用于写入顺序的同步屏障中的分组中可能存在位。 其他类型的分组可以包括递增1的获取和操作分组，递减1的获取和操作分组，具有清除的获取和操作分组，具有递增1的存储和操作分组，具有递增1的存储和操作分组， 递减1，具有逻辑OR的存储和操作分组以及具有逻辑AND的存储和操作分组。

公开(公告)号：US5784569A

公开(公告)日：1998-07-21

申请号：US717581

申请日：1996-09-23

申请人： Steven C. Miller ,  Jamie Riotto ,  James E. Tornes ,  Ross G. Werner

发明人： Steven C. Miller ,  Jamie Riotto ,  James E. Tornes ,  Ross G. Werner

IPC分类号： G06F13/362 ,  G06F13/366 ,  H04N7/173 ,  G06F17/00

CPC分类号： H04N7/17336 ,  G06F13/3625 ,  G06F13/366

摘要： The present invention discloses a novel arbitration procedure for selecting among devices in a computer system requesting access to a single resource such as, for example, a system bus or main memory. The arbitration procedure provides an efficient means for guaranteeing the available system bus bandwidth to devices having high bandwidth requirements. Each device can be allotted a certain amount of bandwidth that is guaranteed to be available for that device within a given time interval. Excess bandwidth not consumed by the guaranteed allotments can be used as remainder (e.g., available but not guaranteed) bandwidth by the devices. The arbitration procedure further provides a guaranteed maximum latency so that no device is prevented from completing data transfers in a timely manner. The arbitration procedure still further provides the ability to dynamically program the amount of the bandwidth that is guaranteed a particular device. The arbitration procedure can be applied to a number of different communication platforms and bus protocols.

摘要翻译： 本发明公开了一种用于在计算机系统中的设备之间进行选择的新颖的仲裁程序，该计算机系统请求访问诸如系统总线或主存储器的单个资源。 仲裁程序提供了一种有效的手段，用于为具有高带宽要求的设备保证可用的系统总线带宽。 每个设备可以在给定的时间间隔内分配一定数量的带宽，保证该设备可用。 由保证分配不消耗的过量带宽可以被设备用作剩余（例如可用但不能保证）的带宽。 仲裁程序进一步提供有保证的最大等待时间，从而防止任何设备及时完成数据传输。 仲裁程序还提供了动态地编程保证特定设备的带宽量的能力。 仲裁程序可以应用于许多不同的通信平台和总线协议。

公开(公告)号：US06622182B1

公开(公告)日：2003-09-16

申请号：US09409805

申请日：1999-09-30

申请人： Steven C. Miller ,  James E. Tornes

发明人： Steven C. Miller ,  James E. Tornes

IPC分类号： G06F1314

CPC分类号： G06F3/14

摘要： A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. The system also includes an efficient return channel to minimizine the amount of data transfer bandwidth required in returning status information on the FIFO buffer of the input/output unit. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.

摘要翻译： 一种用于控制计算机控制的图形系统内的输入/输出单元的信息流（例如，图形基元，显示数据等）的方法和装置。 该系统包括具有先进先出（FIFO）缓冲器，具有其FIFO缓冲器的单独输入/输出单元和耦合在输入/输出单元与多个FIFO缓冲器之间的多个中间设备（具有FIFO缓冲器） 处理器，用于将输入/输出数据从处理器移动到输入/输出单元。 机制放置在一个中间装置中，该中间装置保持对输入/输出单元发送的输入/输出数据的计数，但尚未从输入/输出单元的缓冲器中清除。 这些机制调节到输入/输出单元的数据流。 该系统还包括有效的返回通道，以最小化返回输入/输出单元的FIFO缓冲器上的状态信息所需的数据传输带宽量。 当输入/输出单元和/或中间设备拥塞时，系统还包括有效地调用定时器机制，用于暂时将处理器从发送存储发送到输入/输出单元。 在定时器机制超时之后，处理器不会被中断请求中断，从而允许系统在需要长时间调用中断之前清除其拥塞。

公开(公告)号：US06985484B1

公开(公告)日：2006-01-10

申请号：US09896370

申请日：2001-06-28

申请人： Steven C. Miller ,  James E. Tornes

发明人： Steven C. Miller ,  James E. Tornes

IPC分类号： H04L12/28 ,  H04J3/22

CPC分类号： H04L49/253 ,  H04L49/30

摘要： A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet. In addition, there may be bits within a packet used to indicate a coherent transaction, guarantee bandwidth, an error during transmission, or a sync barrier for write ordering. Other types of packets may include a fetch and operation packet with increment by one, a fetch and operation packet with decrement by one, a fetch and operation packet with clear, a store and operation packet with increment by one, a store and operation packet with decrement by one, a store and operation packet with a logical OR, and a store and operation packet with a logical AND.

摘要翻译： 一种用于在耦合到所述交换路由器的多个设备之间并发地发送分组化数据的交换路由器。 这些设备耦合到交换路由器的I / O端口。 然后将交换路由器编程为将数据包从各种源端口路由到多个目的端口。 可以通过交换路由器同时发送不同的分组。 分组由包含对应于分组路由，数据格式，大小和事务标识的信息的命令字组成。 此外，命令字可以包括用于将分组路由到目的地设备的目的地标识号，目的地设备用于发送回应用的源标识号，用于标记需要响应的请求的事务号，以及分组类型值 指示特定类型的数据包。 此外，在用于指示相干事务，保证带宽，传输期间的错误或用于写入顺序的同步屏障中的分组中可能存在位。 其他类型的分组可以包括递增1的获取和操作分组，递减1的获取和操作分组，具有清除的获取和操作分组，具有递增1的存储和操作分组，具有递增1的存储和操作分组， 递减1，具有逻辑OR的存储和操作分组以及具有逻辑AND的存储和操作分组。

公开(公告)号：US06683876B1

公开(公告)日：2004-01-27

申请号：US08717580

申请日：1996-09-23

申请人： James E. Tornes ,  Steven C. Miller ,  Daniel Yau ,  Jamie Riotto

发明人： James E. Tornes ,  Steven C. Miller ,  Daniel Yau ,  Jamie Riotto

IPC分类号： H04L1256

CPC分类号： H04L49/30 ,  H04L49/101 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3018

摘要： A novel packet switched routing architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are coupled to a central packet switched router via links. Due to the nature of these tightly coupled links, high data rates can be achieved between devices and the packet switched router with minimal pins. Any device can communicate to any other device via the packet switched router. The packet switched router has the capability of establishing multiple communication paths at the same time. Hence, multiple communications can occur simultaneously, thereby significantly increasing the overall system bandwidth.

摘要翻译： 一种新颖的分组交换路由架构，用于在多个设备之间建立多个并发通信。 任何数量的设备经由链路耦合到中央分组交换路由器。 由于这些紧密耦合的链路的性质，可以在设备和具有最小引脚的分组交换路由器之间实现高数据速率。 任何设备都可以通过分组交换路由器与任何其他设备进行通信。 分组交换路由器具有同时建立多条通信路径的能力。 因此，可以同时发生多个通信，从而显着增加整个系统带宽。

公开(公告)号：US6154794A

公开(公告)日：2000-11-28

申请号：US716951

申请日：1996-09-08

申请人： Karim M. Abdalla ,  Kianoosh Naghshineh ,  James E. Tornes ,  Daniel Yau

发明人： Karim M. Abdalla ,  Kianoosh Naghshineh ,  James E. Tornes ,  Daniel Yau

IPC分类号： G06F3/14 ,  G06F13/14 ,  G06F13/20

CPC分类号： G06F3/14

摘要： A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. By placing these mechanisms close to the processor, rather than within the input/output unit, the system allows a larger portion of the input/output unit's buffer to be utilized for storing input/output data before a processor suspend or interrupt is required. This leads to increased input/output data throughput between the processor and the input/output unit by reducing processor interrupts. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.

摘要翻译： 一种用于控制计算机控制的图形系统内的输入/输出单元的信息流（例如，图形基元，显示数据等）的方法和装置。 该系统包括具有先进先出（FIFO）缓冲器，具有其FIFO缓冲器的单独输入/输出单元和耦合在输入/输出单元与多个FIFO缓冲器之间的多个中间设备（具有FIFO缓冲器） 处理器，用于将输入/输出数据从处理器移动到输入/输出单元。 机构位于非常接近处理器的中间设备内，其维持对输入/输出单元发送的输入/输出数据的数量的记账，但尚未从输入/输出单元的缓冲器中清除。 这些机制调节到输入/输出单元的数据流。 通过将这些机制放置在处理器附近，而不是在输入/输出单元内，系统允许输入/输出单元的缓冲区的较大部分用于在处理器挂起或中断之前存储输入/输出数据。 这导致通过减少处理器中断来增加处理器和输入/输出单元之间的输入/输出数据吞吐量。 当输入/输出单元和/或中间设备拥塞时，系统还包括有效地调用定时器机制，用于暂时将处理器从发送存储发送到输入/输出单元。 在定时器机制超时之后，处理器不会被中断请求中断，从而允许系统在需要长时间调用中断之前清除其拥塞。