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    TRAFFIC SCHEDULING METHOD AND APPARATUS, AND ELECTRONIC DEVICE AND COMPUTER-READABLE MEDIUM
    1.
    发明公开
    TRAFFIC SCHEDULING METHOD AND APPARATUS, AND ELECTRONIC DEVICE AND COMPUTER-READABLE MEDIUM 审中-公开

    公开(公告)号：US20240121202A1

    公开(公告)日：2024-04-11

    申请号：US18546102

    申请日：2022-01-04

    Applicant: BEIJING HUIJUN TECHNOLOGY CO., LTD.

    Inventor： Xuqian LI ,  Bin DONG ,  Li LI

    IPC: H04L49/253

    CPC classification number: H04L49/253

    Abstract: The present disclosure relates to a traffic scheduling method and apparatus, and an electronic device and a computer-readable medium. The traffic scheduling method comprises: acquiring, by means of a traffic egress switch, a current packet to be sent, and forwarding the packet to a programmable switch, which is connected to the traffic egress switch; acquiring, by means of the programmable switch, a communication parameter corresponding to the packet, and determining a target port identifier of the packet according to the communication parameter; marking the packet according to the target port identifier of the packet, and returning the marked packet to the traffic egress switch; and determining, according to the target port identifier, a target output port corresponding to the packet from among a plurality of output ports of the traffic egress switch, and sending the packet by means of the target output port.

    SYSTEMS, METHODS, AND DEVICES FOR INTERCONNECTING NETWORK DEVICES
    2.
    发明公开
    SYSTEMS, METHODS, AND DEVICES FOR INTERCONNECTING NETWORK DEVICES 审中-公开

    公开(公告)号：US20240015115A1

    公开(公告)日：2024-01-11

    申请号：US17862068

    申请日：2022-07-11

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Shai Cohen

    IPC: H04L49/15 ,  H04L49/253 ,  H04L49/00

    CPC classification number: H04L49/15 ,  H04L49/253 ,  H04L49/30

    Abstract: An apparatus for interconnecting devices in a network comprises a connection interface with a first face and a second face opposite the first face. The apparatus includes a first 2D array of first connection points arranged on the first face of the connection interface. Each first connection point in each column of the first 2D array connects to a different host device from among a plurality of host devices, and each first connection point in each row of the first 2D array connects to a single host device from among the plurality of host devices. A second 2D array of second connection points is arranged on the second face of the connection interface. Each second connection point is connected to a respective first connection point, each second connection point in each column of the second 2D array connects to a single network switch from among a plurality of network switches, and each second connection point in each row of the second 2D array connects to a different network switch from among the plurality of network switches.

    Large-scale network with high port utilization
    6.
    发明授权
    Large-scale network with high port utilization 有权

    公开(公告)号：US11765103B2

    公开(公告)日：2023-09-19

    申请号：US17539252

    申请日：2021-12-01

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Michael Gandelman ,  Jose Yallouz

    IPC: H04L49/253 ,  H04L49/10 ,  H04L45/02 ,  H04L49/00

    CPC classification number: H04L49/253 ,  H04L45/04 ,  H04L49/10 ,  H04L49/30 ,  H04L49/70

    Abstract: A data communication system includes a plurality of mutually-disjoint sets of switches, each set including multiple mutually-disjoint subsets of the switches in the set. Local links interconnect the switches within each of the subsets in a fully-connected topology, while none of the switches in any given subset are connected in a single hop to any of the switches in any other subset within the same set. Global links interconnect the sets of the switches, each global link connecting one switch in one of the sets to another switch in another one of the sets, such that each of the subsets in any given set of the switches is connected in a single hop by at least one global link to at least one of the subsets of every other set of the switches.

    Large-scale network with high port utilization
    8.
    发明公开
    Large-scale network with high port utilization 审中-公开

    公开(公告)号：US20230171206A1

    公开(公告)日：2023-06-01

    申请号：US17539252

    申请日：2021-12-01

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Michael Gandelman ,  Jose Yallouz

    IPC: H04L49/253 ,  H04L49/10 ,  H04L49/00 ,  H04L45/00

    CPC classification number: H04L49/253 ,  H04L49/10 ,  H04L49/30 ,  H04L49/70 ,  H04L45/04

    Abstract: A data communication system includes a plurality of mutually-disjoint sets of switches, each set including multiple mutually-disjoint subsets of the switches in the set. Local links interconnect the switches within each of the subsets in a fully-connected topology, while none of the switches in any given subset are connected in a single hop to any of the switches in any other subset within the same set. Global links interconnect the sets of the switches, each global link connecting one switch in one of the sets to another switch in another one of the sets, such that each of the subsets in any given set of the switches is connected in a single hop by at least one global link to at least one of the subsets of every other set of the switches.

    COMMUNICATION LOOP PREVENTION IN AN INFORMATION HANDLING SYSTEM
    9.
    发明申请
    COMMUNICATION LOOP PREVENTION IN AN INFORMATION HANDLING SYSTEM 审中-公开

    公开(公告)号：US20180254985A1

    公开(公告)日：2018-09-06

    申请号：US15447208

    申请日：2017-03-02

    Applicant: DELL PRODUCTS, L.P.

    Inventor： LEE E. BALLARD ,  MICHAEL E. BROWN

    IPC: H04L12/753 ,  H04L12/775 ,  H04L12/937 ,  H04L12/24

    CPC classification number: H04L45/48 ,  H04L41/12 ,  H04L45/583 ,  H04L49/253 ,  H04L49/70

    Abstract: A method, an information handling system (IHS) and a switching system for preventing communication loops in an IHS. The method includes identifying, via a controller, at least one stacking port in a first switch of a first chassis. The first switch is in communication with a second switch of a second chassis via a first link. At least one stacking port is configured as an unblocked port. Port blocking and unblocking actions are determined for the at least one stacking port. The at least one stacking port is configured based on the determined port blocking and unblocking actions and a determination is made if the first chassis is a root bridge chassis having at least one uplink port. In response to the first chassis being a root bridge chassis, a first uplink port in the first switch is configured as an unblocked port.

    NETWORK DEVICE
    10.
    发明申请
    NETWORK DEVICE 审中-公开

    公开(公告)号：US20180241698A1

    公开(公告)日：2018-08-23

    申请号：US15753471

    申请日：2016-08-25

    Applicant: New H3C Technologies Co., Ltd

    Inventor： Zhiyu ZHAO

    IPC: H04L12/931 ,  H04L12/937 ,  H04L12/24 ,  H04L12/721 ,  G06F13/38

    CPC classification number: H04L49/40 ,  G06F11/2002 ,  G06F13/385 ,  G06F13/4022 ,  G06F2213/0026 ,  H04L41/0806 ,  H04L45/38 ,  H04L49/253

    Abstract: A network device may include a first forwarding board, a second forwarding board and an interface board. The interface board may include a control apparatus and a network interface chip. The control apparatus may form a first upstream packet flow which is sent to the first forwarding board via a first I/O bus and a second upstream packet flow which is sent to the second forwarding board via a second I/O bus using data packets received through the network interface chip from the exterior of the network device. The control apparatus may selectively connect one of a first downstream packet flow and a second downstream packet flow to the network interface chip through the network interface bus according to an active/standby state of the first forwarding board and the second forwarding board, wherein the first downstream packet flow is processed by the first forwarding board and received through the first I/O bus and the second downstream packet flow is processed by the second forwarding board and received through the second I/O bus.

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