公开(公告)号：US07437590B2

公开(公告)日：2008-10-14

申请号：US11404495

申请日：2006-04-14

申请人： Steven Decker ,  Jianrong Chen ,  David P. Foley ,  Mark T. Sayuk

发明人： Steven Decker ,  Jianrong Chen ,  David P. Foley ,  Mark T. Sayuk

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08

CPC分类号： H04B15/04 ,  H03K3/84 ,  H03K5/156 ,  H03K7/06 ,  H03L7/0812

摘要： A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so that the synthesized clock signal is a spread-spectrum clock signal and/or a clock signal having a nominal frequency that is greater than a nominal frequency of each of the input clock signals.

摘要翻译： 状态机电路可以用于控制多路复用电路，其选择并提供多个输入时钟信号中的相应输入时钟信号给响应于这种输入时钟信号产生合成时钟信号的时钟合成电路。 例如，状态机电路可以被配置为使得合成时钟信号是扩频时钟信号和/或具有大于每个输入时钟信号的标称频率的额定频率的时钟信号。