公开(公告)号：US20060176745A1

公开(公告)日：2006-08-10

申请号：US10906147

申请日：2005-02-04

申请人： Steven Eustis ,  James Monzel ,  Steven Oakland ,  Michael Ouellette

发明人： Steven Eustis ,  James Monzel ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G11C29/00

CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/3202

摘要： A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is further configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of the memory logic connection at the customer chip, wherein test elements of the memory structure comprise a scan architecture of a first type, and test elements of the customer chip comprise a scan architecture of a second type.

摘要翻译： 配置用于支持多种测试方法的存储器结构包括：第一多个复用器，被配置为选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应的内部存储器连接之间的至少一个地址路径。 第二多路复用器被配置用于在功能存储器阵列连接和耦合到所述至少一个数据输入路径的存储器逻辑连接之间选择性地耦合测试锁存器的输入，测试锁存器的输出定义数据输出客户连接。 冲洗逻辑还被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，从而有助于观察客户芯片处的存储器逻辑连接，其中存储器结构的测试元件 包括第一类型的扫描架构，并且客户芯片的测试元件包括第二类型的扫描架构。