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1.发明授权Method and apparatus for equalizing grants of a data bus to primary and secondary devices 失效用于将数据总线授予主要和次要设备的方法和装置
公开(公告)号：US5805836A
公开(公告)日：1998-09-08
申请号：US762901
申请日：1996-12-10
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
CPC分类号： G06F13/364 , G06F13/4031
摘要： An apparatus for equalizing grants of a primary bus to a plurality of primary devices and secondary devices is provided. The apparatus comprises a primary bus bridge to arbitrate grants of the primary bus among a plurality of primary devices attached to the primary bus and a secondary bus bridge to arbitrate grants of the primary bus among a plurality of secondary devices attached to a secondary bus. A logic device is also provided to equalize grants of the primary bus to the primary and the secondary devices.
摘要翻译： 提供了一种用于将主总线的授权均衡到多个主设备和辅助设备的设备。 该装置包括主总线桥，用于在连接到主总线的多个主设备中仲裁主总线的授权，以及辅助总线桥，用于在附加到辅助总线的多个辅助设备中仲裁主总线的授权。 还提供了一个逻辑设备，用于将主总线的授权与主设备和辅助设备相等。
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2.发明授权Method and system for detecting phase-locked loop (PLL) clock synthesis faults 失效用于检测锁相环（PLL）时钟合成故障的方法和系统公开(公告)号：US06895525B1
公开(公告)日：2005-05-17
申请号：US09378425
申请日：1999-08-20
CPC分类号： H03L7/16
摘要： An electronic system includes a reference clock that generates a reference clock signal, at least one, phase-locked loop clock generator that synthesizes a derivative clock signal from the reference clock signal, and at least one digital circuit timed by the derivative clock signal. In addition, the electronic system includes a phase-locked loop clock synthesis fault detector having a phase detector and data storage for storing a historical indication of the phase of the derivative clock signal synthesized from the reference clock signal. The phase detector detects a change of phase of the derivative clock signals relative to the historical indication of the phase and, in response to this detection, signals that a clock synthesis fault has occurred.
摘要翻译： 电子系统包括产生参考时钟信号的参考时钟，至少一个合成来自基准时钟信号的微分时钟信号的锁相环时钟发生器和由导数时钟信号定时的至少一个数字电路。 此外，电子系统包括具有相位检测器和数据存储器的锁相环时钟合成故障检测器，用于存储从参考时钟信号合成的微分时钟信号的相位的历史指示。 相位检测器相对于相位的历史指示器检测导数时钟信号的相位变化，并且响应于该检测，发生时钟合成故障已经发生的信号。
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