公开(公告)号：US6134516A

公开(公告)日：2000-10-17

申请号：US19384

申请日：1998-02-05

申请人： Steven Wang ,  Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Ren-Song Tsay ,  Richard Yachyang Sun ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai

发明人： Steven Wang ,  Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Ren-Song Tsay ,  Richard Yachyang Sun ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022 ,  G06F17/5027

摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.

摘要翻译： SEMulation系统提供四种操作模式：（1）软件仿真，（2）通过硬件加速模拟，（3）在线仿真（ICE）和（4）后仿真分析。 在高水平上，本发明可以以上述四种模式或这些模式的各种组合来体现。 这些模式的核心是控制该系统整体运行的软件内核。 内核的主控制循环执行以下步骤：初始化系统，评估主动测试台过程/组件，评估时钟组件，检测时钟边沿，更新寄存器和存储器，传播组合组件，提前模拟时间，并继续循环 只要存在有效的测试台过程。 根据本发明的实施例的仿真服务器允许多个用户访问相同的可重配置硬件单元，以在网络和非网络环境中以时间共享的方式有效地模拟和加速相同或不同的用户设计。 服务器提供多个用户或进程来访问可重新配置的硬件单元，以实现加速和硬件状态交换的目的。 模拟服务器包括调度程序，一个或多个设备驱动程序和可重新配置的硬件单元。 模拟服务器中的调度器基于抢占式循环算法。 服务器调度程序包括模拟作业队列表，优先级排序器和作业交换器。

公开(公告)号：US6009256A

公开(公告)日：1999-12-28

申请号：US850136

申请日：1997-05-02

申请人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Richard Yachyang Sun ,  Mike Mon Yen Tsai ,  Ren-Song Tsay ,  Steven Wang

发明人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Richard Yachyang Sun ,  Mike Mon Yen Tsai ,  Ren-Song Tsay ,  Steven Wang

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5027 ,  G06F17/5022

摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model's register, send data from the primary clock register to the hardware model's register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model's registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.

公开(公告)号：US08244512B1

公开(公告)日：2012-08-14

申请号：US09954989

申请日：2001-09-12

申请人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai ,  Steven Wang

发明人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai ,  Steven Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5027 ,  G06F2217/86

摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

摘要翻译： 本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。 这个特定的FPGA器件被称为行为处理器。 该行为处理器以硬件方式执行先前在软件中执行的代码结构。 当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应 。

公开(公告)号：US09195784B2

公开(公告)日：2015-11-24

申请号：US13078786

申请日：2011-04-01

申请人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai ,  Steven Wang

发明人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai ,  Steven Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5027 ,  G06F17/5031 ,  G06F2217/68 ,  G06F2217/84 ,  G06F2217/86

摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

摘要翻译： 本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。 这个特定的FPGA器件被称为行为处理器。 该行为处理器以硬件方式执行先前在软件中执行的代码结构。 当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应 。

公开(公告)号：US20110307233A1

公开(公告)日：2011-12-15

申请号：US13078786

申请日：2011-04-01

申请人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai ,  Steven Wang

发明人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai ,  Steven Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5027 ,  G06F17/5031 ,  G06F2217/68 ,  G06F2217/84 ,  G06F2217/86

摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

摘要翻译： 本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。 这个特定的FPGA器件被称为行为处理器。 该行为处理器以硬件方式执行先前在软件中执行的代码结构。 当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应 。