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    Dynamic Flow Segregation for Optimal Load Balancing Among Ports in an Etherchannel Group
    1.
    发明申请
    Dynamic Flow Segregation for Optimal Load Balancing Among Ports in an Etherchannel Group 审中-公开
    在以太通道组中端口之间的最佳负载平衡的动态流隔离

    公开(公告)号：US20120307641A1

    公开(公告)日：2012-12-06

    申请号：US13118664

    申请日：2011-05-31

    申请人： Subbarao Arumilli ,  Prakash Appanna ,  Srihari Shoroff

    发明人： Subbarao Arumilli ,  Prakash Appanna ,  Srihari Shoroff

    IPC分类号： H04L12/26 ,  H04L12/56

    CPC分类号： H04L47/125 ,  H04L43/0882 ,  H04L43/16 ,  H04L47/52

    摘要： Dynamic load balancing techniques among ports of a network device are provided. At a device configured to forward packets in a network, a plurality of queues are generated, each associated with a corresponding one of a plurality of output ports of the device and from which packets are to be output from the device into the network. When the number of packets in the at least one queue exceeds a threshold, for new packets that are to be enqueued to the at least one queue, packets are enqueued to a plurality of sub-queues such that packets are assigned to different ones of the plurality of sub-queues. Each of the plurality of sub-queues is associated with a corresponding one of the plurality of output ports. Packets of the plurality of sub-queues are output from corresponding ones of the plurality of output ports.

    摘要翻译： 提供网络设备端口之间的动态负载均衡技术。 在被配置为在网络中转发分组的设备上，生成多个队列，每个队列与设备的多个输出端口中的相应一个输出端口相关联，并且从该设备将该分组从设备输出到网络中。 当至少一个队列中的分组数量超过阈值时，对于要排队到至少一个队列的新分组，分组排队到多个子队列，使得分组被分配给不同的队列 多个子队列。 多个子队列中的每一个与多个输出端口中的对应的一个相关联。 从多个输出端口中的相应的输出端口输出多个子队列的分组。

    Integrated logic circuit including impedance fault detection
    2.
    发明授权
    Integrated logic circuit including impedance fault detection 失效
    集成逻辑电路包括阻抗故障检测

    公开(公告)号：US5383194A

    公开(公告)日：1995-01-17

    申请号：US973069

    申请日：1992-11-06

    申请人： Mark D. Sloan ,  William A. Rogers ,  Srihari Shoroff

    发明人： Mark D. Sloan ,  William A. Rogers ,  Srihari Shoroff

    IPC分类号： G01R31/30 ,  G11C29/00

    CPC分类号： G01R31/30

    摘要： An integrated logic circuit according to the present invention includes a plurality of logic circuit elements, such as field effect transistors, for performing a combinational logic function, and at least one test controlled-impedance element for loading the logic circuit and causing a first digital output signal to be produced when the impedance of a logic circuit element under test is within a predetermined range and produce another digital output signal when the impedance of the logic circuit element under test is outside the predetermined range. The test controlled-impedance elements typically comprise field effect transistors and are sized in accordance with a series of constraints. The constraints are obtained by considering the operation of the circuit under various impedance fault conditions (high, low and intermediate) and deriving a series of size relationships between the impedance values of the logic circuit and test elements. The impedance faults capable of being detected include the conventional stuck-on (LIF) arid stuck-off (HIF) impedance faults and also intermediate impedance faults (IHIF, ILIF) caused by a too high or too low an impedance in a transistor's on- and off-state modes of operation, respectively.

    摘要翻译： 根据本发明的集成逻辑电路包括用于执行组合逻辑功能的多个逻辑电路元件，例如场效应晶体管，以及至少一个用于加载逻辑电路并产生第一数字输出的测试受控阻抗元件 当被测逻辑电路元件的阻抗在预定范围内时产生的信号，并且当被测逻辑电路元件的阻抗在预定范围之外时产生另一数字输出信号。 测试控制阻抗元件通常包括场效应晶体管，并且根据一系列约束来定尺寸。 通过考虑电路在各种阻抗故障条件（高，低和中等）条件下的操作并得出逻辑电路和测试元件的阻抗值之间的一系列尺寸关系，可以获得约束。 能够检测到的阻抗故障包括常规的固定（LIF）干扰（HIF）阻抗故障以及由晶体管导通时阻抗过高或过低引起的中间阻抗故障（IHIF，ILIF） 和离态操作模式。