公开(公告)号：US20060255379A1

公开(公告)日：2006-11-16

申请号：US11432836

申请日：2006-05-11

Applicant: Subhas Chandra Veeramma

Inventor： Subhas Chandra Veeramma

IPC: H01L29/76

CPC classification number: H01L29/8611 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/66136

Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.

Abstract translation: 在芯片上定义二极管。 该二极管包括具有上表面和下表面的P导电性基片，该基片具有对应于模具的第一和第二边缘的第一和第二端。 阳极接触基板的下表面。 在基板的上表面设置有N导电层，该层具有上表面和下表面。 在该层的上部形成N导电性的掺杂区域。 阴极接触掺杂区域。 钝化层设置在层的上表面上并靠近阴极。

公开(公告)号：US20060246642A1

公开(公告)日：2006-11-02

申请号：US11380466

申请日：2006-04-27

Applicant: Subhas Chandra Veeramma

Inventor： Subhas Chandra Veeramma

IPC: H01L21/8234

CPC classification number: H01L29/402 ,  H01L23/3171 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/66128 ,  H01L29/7811 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N− type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method. First and second electrodes are coupled to the N− type silicon region and the N+ type silicon region, respectively. The oxide layer has a thickness 0.5 to 3 microns. The power device also includes a polymide layer having a thickness of 3 to 20 microns; a first field plate overlying the oxide layer; and second field plate overlying the polymide layer and the first field plate, wherein the second field plate overlaps the first field plate by 2 to 15 microns.

Abstract translation: 半导体功率器件包括半导体衬底。 衬底包括N型硅区和N +硅区。 氧化物层覆盖N-型硅区域，使用等离子体增强化学气相沉积（PECVD）方法形成氧化物层。 第一和第二电极分别耦合到N型硅区和N +型硅区。 氧化物层的厚度为0.5至3微米。 功率器件还包括厚度为3至20微米的聚酰亚胺层; 覆盖氧化物层的第一场板; 以及覆盖所述聚酰亚胺层和所述第一场板的第二场板，其中所述第二场板与所述第一场板重叠2至15微米。