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1.发明申请公开(公告)号：US20080195984A1
公开(公告)日：2008-08-14
申请号：US12104852
申请日：2008-04-17
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design.Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.
摘要翻译： 随着芯片复杂度的增加，VLSI芯片的可路由性（或布线拥塞）变得越来越重要。 拥塞对性能，产量和芯片面积有重大影响。 本发明在物理设计之前针对技术独立综合早期拥塞的优化。 我们不是试图优化逻辑结构以及电路的空间布局，而是将这样的优化限制在逻辑综合的范围之内。 也就是说，我们提出了一种积极的优化方法，在技术独立合成中识别电路结构，并产生更可预测的实现，从而提供更好的可路由性和产量。
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公开(公告)号：US4259367A
公开(公告)日：1981-03-31
申请号：US61951
申请日：1979-07-30
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/48 , H01L21/768 , H01L23/525 , H05K3/22 , H05K3/46 , H01L21/28
CPC分类号： H01L21/4814 , H01L21/76892 , H01L23/525 , H05K3/225 , H01L2924/0002 , H05K2203/173 , H05K2203/175 , H05K3/4685
摘要： Repair of opens and shorts in semiconductor packages and chip metallurgy by initial conversion of shorts into opens by severing of lines about the shorts, followed by interconnection of conductor patch lines to the good circuit portions through an insulating layer.
摘要翻译： 通过切断短路线，然后通过绝缘层将导体贴片线互连到良好的电路部分，通过将短路初始转换成开路来修复半导体封装中的开路和短路以及芯片冶金。
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3.发明授权Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers 失效具有内部导体图案的多层电介质平面结构，其特征在于设置在层的公共边缘表面处的相对端子
公开(公告)号：US4202007A
公开(公告)日：1980-05-06
申请号：US918213
申请日：1978-06-23
IPC分类号： H05K3/46 , H01L23/498 , H01L23/538 , H05K1/00 , H01L39/02 , H01L23/48 , H01L29/44
CPC分类号： H01L23/5383 , H01L23/49822 , H05K1/0298 , H01L2924/09701 , H01L2924/15174 , H01L2924/15192 , H01L2924/15312 , H01L2924/3011
摘要： The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The conductor runs are returned through the body to the active face of the body to position the opposite or distal ends of the conductors thereat, in an increased spaced relationship of the distal conductor terminations. For external connection, terminal pins may be embedded in the fired body for connection at adjacent and to the distal conductor termination, with the pins projecting therefrom.
摘要翻译： 将电介质生片上的导体图案涂覆到其公共边缘上，其中堆叠或叠加多个片材以包围导体图案，随后烧结，其中具有暴露端端的烧制体的边缘侧变为实际 电路中连接有半导体器件的主体的表面，其中导线连接到相应的公共末端。 导体延伸通过主体返回到主体的主动面，以将导体的相对或远端定位在远端导体终端的增加的间隔关系中。 对于外部连接，端子引脚可以嵌入在烧制体中，用于在相邻端和远端导体端子处连接，其中引脚从其突出。
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公开(公告)号：US4193082A
公开(公告)日：1980-03-11
申请号：US918214
申请日：1978-06-23
申请人： William E. Dougherty
发明人： William E. Dougherty
IPC分类号： H01L23/498 , H01L23/538 , H05K1/00 , H01L39/02
CPC分类号： H01L23/5383 , H01L23/49822 , H05K1/0298 , H01L2224/16 , H01L2224/16235 , H01L2924/01322 , H01L2924/09701 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011
摘要： The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The opposite or distal ends of the conductor runs may be fanned out to the opposite edge of side of the fired body in increased spaced relationship to each other.
摘要翻译： 将电介质生片上的导体图案涂覆到其公共边缘上，其中堆叠或叠加多个片材以包围导体图案，随后烧结，其中具有暴露端端的烧制体的边缘侧变为实际 电路中连接有半导体器件的主体的表面，其中导线连接到相应的公共末端。 导体延伸的相对端或远端可以以相互间隔开的间隔开的方式扇形到烧制体的侧面的相对边缘。
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5.发明申请Method for Enabling Multiple Incompatible or Costly Timing Environments for Efficient Timing Closure 有权启用多个不兼容或成本高的定时环境以实现高效定时关闭的方法公开(公告)号：US20120144357A1
公开(公告)日：2012-06-07
申请号：US12958431
申请日：2010-12-02
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
摘要翻译： 基于松弛值执行静态时序分析以验证和优化逻辑设计的方法包括：在所述逻辑设计内选择具有至少两个输入的已知值的一个或多个电路; 识别从所述已知值的输入中控制所选择的电路的输出到达时间的关键输入; 基于关键和非关键输入的到达时间之间的差异，确定电路的一个或多个非关键输入的所需到达时间; 并且基于关键和非关键输入的AT之间的差异来计算关键输入上的松弛。 基于由到达时间差定义的松弛的设计优化优选地使用反向合并边缘设计度量。 该度量确定时钟整形电路的非关键信号的输入到达时间的确切需要量的改善。
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6.发明申请METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATION AND SLACK CATEGORIZATION 有权用于通过变换和滑动分类来消除网络中的负面滑块的方法公开(公告)号：US20090070715A1
公开(公告)日：2009-03-12
申请号：US11853573
申请日：2007-09-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
摘要翻译： 用于消除表示芯片设计的网表中的负松弛的方法使用设计的定时环境来在逻辑和物理合成阶段将信息叠加到设计环境上。 重叠的定时信息确定哪个网表转换为负消除消除提供了最大的杠杆作用，以及为每个设计调整的创建动态变换配方的方法。 该方法进一步提供消极消除的上限，以防止网表变换被应用于超出改进设计能力的情况。
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7.发明授权Method for providing improved electrical and mechanical connection between I/O pin and transverse via substrate 失效用于在I / O引脚和横向通孔基板之间提供改进的电气和机械连接的方法
公开(公告)号：US4598470A
公开(公告)日：1986-07-08
申请号：US713569
申请日：1985-03-18
CPC分类号： H05K3/32 , H01R43/205 , H05K3/308 , H05K1/0306 , H05K2201/09854 , H05K2201/10303 , H05K2201/1059 , H05K2203/1189 , Y10T29/4913 , Y10T29/49139
摘要： A method of making an aperture of a predetermined shape into a dielectric substrate which will lockingly receive a deformable contact pin. It includes providing a dielectric material which shrinks in response to a heat treatment by an amount which is different in one direction from that in another direction, and which irreversibly changes dimensions in its two orthogonal directions in proportion to this difference. An aperture is formed in such a material, in a direction normal to the plane of the two orthogonal directions and the material is subjected to a heat treatment that causes a differential shrinkage in the aperture and a change in the shape of the aperture. A deformable contact pin is then forced into a locking position in the aperture. By using such a method to lock a contact pin in close proximity to a conductive line extending across the substrate or by having the aperture and the pin extend through the substrate, electrical circuits on one side of the substrate can be contacted through a contact pin on the opposite side of the substrate.
摘要翻译： 将预定形状的孔径制造成将锁定地容纳可变形接触销的电介质基片的方法。 它包括提供一种电介质材料，该电介质材料响应于热处理而收缩的量在一个方向上与另一个方向上的量不同，并且在该两个正交方向上不均匀地改变尺寸与该差异成比例。 在这样的材料中，沿垂直于两个正交方向的平面的方向形成孔，并且材料经受热处理，导致孔径不均匀收缩和孔的形状变化。 然后可变形接触销被迫进入孔中的锁定位置。 通过使用这种方法来将接触销锁紧在延伸穿过衬底的导电线附近，或者通过使孔和引脚延伸穿过衬底，衬底一侧上的电路可以通过接触引脚 衬底的相对侧。
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8.发明授权Method for enabling multiple incompatible or costly timing environment for efficient timing closure 有权用于实现多个不兼容或昂贵的定时环境以实现有效的定时关闭的方法公开(公告)号：US08302049B2
公开(公告)日：2012-10-30
申请号：US12958431
申请日：2010-12-02
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
摘要翻译： 基于松弛值执行静态时序分析以验证和优化逻辑设计的方法包括：在所述逻辑设计内选择具有至少两个输入的已知值的一个或多个电路; 识别从所述已知值的输入中控制所选择的电路的输出到达时间的关键输入; 基于关键和非关键输入的到达时间之间的差异，确定电路的一个或多个非关键输入所需的到达时间; 并且基于关键和非关键输入的AT之间的差异来计算关键输入上的松弛。 基于由到达时间差定义的松弛的设计优化优选地使用反向合并边缘设计度量。 该度量确定时钟整形电路的非关键信号的输入到达时间的确切需要量的改善。
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9.发明授权Method for eliminating negative slack in a netlist via transformation and slack categorization 有权通过转换和松散分类消除网表中的负松弛的方法公开(公告)号：US07810062B2
公开(公告)日：2010-10-05
申请号：US11853573
申请日：2007-09-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.
摘要翻译： 用于消除表示芯片设计的网表中的负松弛的方法使用设计的定时环境来在逻辑和物理合成阶段将信息叠加到设计环境上。 重叠的定时信息确定哪个网表转换为负消除消除提供了最大的杠杆作用，以及为每个设计调整的创建动态变换配方的方法。 该方法进一步提供消极消除的上限，以防止网表变换被应用于超出改进设计能力的情况。
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公开(公告)号：US4602271A
公开(公告)日：1986-07-22
申请号：US682963
申请日：1984-02-15
IPC分类号： H01L23/538 , H01L39/04 , H01L23/02 , H01L23/08
CPC分类号： H01L23/5385 , H01L2924/0002 , H01L2924/15174
摘要： A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.
摘要翻译： 提供用于封装半导体芯片的基板，其由相对端部终止于安装表面的导体和在表面下方延伸的中间部分构成。 导体的端部以沿着基板纵向重复的图案布置，由不具有导体端的正交条分开，以允许密集的表面布线。 重复图案被布置成允许具有足够间隔的芯片安装位置以允许表面布线。 以这种方式，可以通过个性化表面布线和预置的基板导体连接相同和重复图案的芯片。
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