公开(公告)号：US06630860B1

公开(公告)日：2003-10-07

申请号：US09666353

申请日：2000-09-20

申请人： Sudhaker Reddy Anumula ,  Thomas Clark Bryan

发明人： Sudhaker Reddy Anumula ,  Thomas Clark Bryan

IPC分类号： H03K500

CPC分类号： H03H11/1291 ,  H03L7/093

摘要： A programmable phase locked-loop (PLL) active filter circuit is provided which includes networks of cooperating bandwidth tuning components to select bandwidth ranges. The values and arrangement of the network of selectable series input (R1) resistors are chosen to be useful in both low band and high band settings. Likewise, the opamp network of feedback resistors (R2) and capacitors (C1) values are chosen to be useful in both low band and high band applications, automatically pairing with the R1 selection in response to a bandwidth range selection. These tuning components, internal to an integrated circuit, can be used for a plurality of wideband loops. External components can be used to supplement the internal components for low and high bandwidth applications.

摘要翻译： 提供了可编程锁相环（PLL）有源滤波器电路，其包括协作带宽调谐组件的网络以选择带宽范围。 可选串联输入（R1）电阻网络的值和布置被选择为在低频和高频带设置中都有用。 同样，反馈电阻（R2）和电容器（C1）值的运算放大器网络被选择为在低频带和高频带应用中都有用，响应于带宽范围选择自动与R1选择配对。 集成电路内部的这些调谐组件可用于多个宽带环路。 外部组件可用于补充低带宽和高带宽应用的内部组件。

公开(公告)号：US5978280A

公开(公告)日：1999-11-02

申请号：US132100

申请日：1998-08-10

申请人： Satish C. Saripella ,  Jeffery Scott Hunt ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

发明人： Satish C. Saripella ,  Jeffery Scott Hunt ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

IPC分类号： G11C7/06 ,  G11C13/00

CPC分类号： G11C7/06

摘要： A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.

摘要翻译： 一种包括读出放大器，评估电路，控制电路和寄存器电路的电路。 读出放大器电路可以被配置为响应于（i）输入信号和（ii）使能信号而呈现第一输出和第二输出。 评估电路可以被配置为响应于第一和第二输出呈现评估信号。 响应于（i）评估信号和（ii）字线信号，控制电路可以被配置为呈现（i）第一时钟信号，第二时钟信号和使能信号。 寄存器电路可以被配置为响应于第一和第二时钟信号保持第一或第二输出。 寄存器电路可以被实现为可响应于第一和第二时钟信号的主从寄存器。

公开(公告)号：US6016277A

公开(公告)日：2000-01-18

申请号：US884581

申请日：1997-06-27

申请人： George M. Ansel ,  Jeffery S. Hunt ,  Satish Saripella ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

发明人： George M. Ansel ,  Jeffery S. Hunt ,  Satish Saripella ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

IPC分类号： G11C11/00 ,  G11C7/06

CPC分类号： G11C11/005

摘要： A reference voltage generator may include an input for receiving a first voltage for input to a sense amp. The reference voltage generator may also include an output for outputting a second voltage for input to the sense amp. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first bitline. The reference voltage generator may also include a first output for outputting a second voltage on a second bitline. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first transmission busline. The voltage generator may also include a first output for outputting a second voltage on a second transmission busline. The second voltage is influenced by the first voltage.

摘要翻译： 参考电压发生器可以包括用于接收用于输入到感测放大器的第一电压的输入端。 参考电压发生器还可以包括用于输出用于输入到感测放大器的第二电压的输出。 第二电压受第一电压的影响。 或者，参考电压发生器可以包括用于在第一位线上接收第一电压的第一输入。 参考电压发生器还可以包括用于在第二位线上输出第二电压的第一输出。 第二电压受第一电压的影响。 或者，参考电压发生器可以包括用于在第一传输总线上接收第一电压的第一输入。 电压发生器还可以包括用于在第二传输总线上输出第二电压的第一输出。 第二电压受第一电压的影响。

公开(公告)号：US06566967B1

公开(公告)日：2003-05-20

申请号：US10085458

申请日：2002-02-26

申请人： Sudhaker Reddy Anumula ,  Joseph J. Balardeta ,  Wei Fu ,  Paul Vanderbilt ,  Mehmet Mustafa Eker

发明人： Sudhaker Reddy Anumula ,  Joseph J. Balardeta ,  Wei Fu ,  Paul Vanderbilt ,  Mehmet Mustafa Eker

IPC分类号： H03L700

CPC分类号： H03L7/18 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/107 ,  H03L7/113 ,  H03L7/14

摘要： A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.

摘要翻译： 具有多个检测元件的可配置PLL架构。 可配置PLL电路包括用于提供第一差分信号的第一检测器，用于提供第二差分信号的第二检测器，用于提供第三差分信号的第三检测器，以及用于使第一，第二和第 第三检测器。 PLL电路还包括多路复用器，用于从相应的使能检测器接收至少一个差分信号，并提供多路复用的差分信号输出。 在操作中，选择操作模式，并且启用一个或多个检测器以使用一个或多个输入参考信号进行操作。 使能的检测器的输出由多路复用器接收以完成所选择的操作模式的操作。

公开(公告)号：US6041388A

公开(公告)日：2000-03-21

申请号：US804025

申请日：1997-02-19

申请人： Sudhaker Reddy Anumula ,  Ping Wu

发明人： Sudhaker Reddy Anumula ,  Ping Wu

IPC分类号： G11C7/10 ,  G06F13/00

CPC分类号： G11C7/1006

摘要： A memory array having a physical depth of 2N-bits (N being an integer) includes control and data bus logic configured to control read and/or write operation in the memory array and to select the depth of the memory array. The control logic may include upper and lower byte control circuitry and the depth of the array may be selected from a group consisting of xN-bits and 2xN-bits, x being an integer. The control and data bus logic may be implemented as metal options within the device to be selected during fabrication to achieve a desired array depth.

摘要翻译： 具有2N位物理深度（N为整数）的存储器阵列包括被配置为控制存储器阵列中的读取和/或写入操作并选择存储器阵列的深度的控制和数据总线逻辑。 控制逻辑可以包括高字节和低字节控制电路，并且可以从由xN位和2xN位组成的组中选择阵列的深度，x是整数。 控制和数据总线逻辑可以被实现为在制造期间要选择的器件内的金属选项以实现期望的阵列深度。

公开(公告)号：US5880999A

公开(公告)日：1999-03-09

申请号：US884561

申请日：1997-06-27

申请人： George M. Ansel ,  Jeffery S. Hunt ,  Satish Saripella ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

发明人： George M. Ansel ,  Jeffery S. Hunt ,  Satish Saripella ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

IPC分类号： G11C11/00 ,  G11C16/04

CPC分类号： G11C11/005

摘要： A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided. A sense amplifier having a first input coupled to the first output of the column select pass gates and a second input coupled to the second output of the column select pass gates may be included in the memory device. The memory device may be read by modulating a first voltage input to the sense amplifier using a second voltage input to the sense amplifier.

摘要翻译： 存储器件包括通过RAM字线可访问并耦合在第一和第二位线之间的随机存取存储器（RAM）单元; 只读存储器（ROM）单元，可通过ROM字线访问并且具有耦合到第一位线的输出和被配置为接收第一电压信号的输入; 以及参考电压发生器，其具有耦合到第一位线的第一输入，被配置为接收第一电压信号的第二输入和耦合到第二位线的输出。 存储器件还可以包括具有耦合到第一位线的输出的位线负载。 配置为产生第一电压信号的虚拟接地驱动器可以耦合到只读存储器单元的输入。 此外，列选择通道门被配置为处于逻辑信号的控制下，并且具有耦合到第一位线的第一输入，耦合到第二位线的第二输入，第一输出和第二输出。 具有耦合到列选择通过门的第一输出的第一输入和耦合到列选择通道的第二输出的第二输入的读出放大器可以包括在存储器件中。 可以通过使用输入到读出放大器的第二电压调制对读出放大器的第一电压输入来读取存储器件。

公开(公告)号：US07057418B1

公开(公告)日：2006-06-06

申请号：US10823060

申请日：2004-04-13

申请人： Wei Fu ,  Sudhaker Reddy Anumula ,  Hongwen Lu ,  Joseph J. Balardeta

发明人： Wei Fu ,  Sudhaker Reddy Anumula ,  Hongwen Lu ,  Joseph J. Balardeta

IPC分类号： G01R25/00

CPC分类号： H03D13/003 ,  G01R25/005

摘要： A high-speed, half rate phase detector provides an effective solution to the problem of XOR gate response to the minimum width signal precursors (Q1 and Q2) of a phase signal that indicates a phase difference between a data signal and a clock signal by combining the precursor signals in a multiplexer and combining the multiplexed signal with the data signal in an XOR gate. This affords the transition information in the transitions of the precursor signals, which is significant of phase difference, without requiring the XOR gate to respond to the minimum widths of those pulses.

摘要翻译： 高速，半速率相位检测器提供了对相位信号的最小宽度信号前导（Q 1和Q 2）的异或门响应的问题的有效解决方案，该相位信号表示数据信号和时钟信号之间的相位差 通过组合多路复用器中的前驱信号并将复用的信号与数据信号组合在异或门中。 这提供了前驱信号的转变中的转换信息，其相位差是显着的，而不需要XOR门对这些脉冲的最小宽度做出响应。

公开(公告)号：US06720806B1

公开(公告)日：2004-04-13

申请号：US10132463

申请日：2002-04-25

申请人： Allen Carl Merrill ,  Joseph James Balardeta ,  Sudhaker Reddy Anumula

发明人： Allen Carl Merrill ,  Joseph James Balardeta ,  Sudhaker Reddy Anumula

IPC分类号： H03B1900

CPC分类号： H03L7/18 ,  H03K5/00006 ,  H03L2207/10

摘要： Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. The frequency doubler is provided with selection control for programming multiple frequencies.

摘要翻译： 锁相环（PLL）的电路包括参考信号输入和倍频器。 倍频器的输出是具有大约是初始参考信号的两倍的频率并被馈送到PLL的第二参考信号。 倍频器包括具有耦合到倍频器的输入的输入的第一延迟电路; 以及具有耦合到延迟电路的输出的第一输入和耦合到倍频器的输入的第二输入的XOR电路。 倍频器可以包括在第一延迟电路之后串联的一个或多个附加延迟电路，其输出被提供给多路复用器。 多路复用器包括选择信号输入，用于选择要提供给异或电路的至少一个延迟电路的输出。 倍频器允许PLL具有较小的反馈分频比和较高的环路增益，以减少抖动。 倍频器具有用于编程多个频率的选择控制。

公开(公告)号：US06545524B1

公开(公告)日：2003-04-08

申请号：US10085613

申请日：2002-02-26

申请人： Sudhaker Reddy Anumula ,  Wei Fu ,  Joseph J. Balardeta ,  Paul Vanderbilt ,  Allen C. Merrill

发明人： Sudhaker Reddy Anumula ,  Wei Fu ,  Joseph J. Balardeta ,  Paul Vanderbilt ,  Allen C. Merrill

IPC分类号： H03K1762

CPC分类号： H03L7/087 ,  H03L7/0891

摘要： A configurable multiplexing circuit and arrangement suited for phase locked loop applications. The multiplexing circuit includes an EX-OR element, a multiplexer element and a summer element. Each element is configured for receiving a particular type of detection signal output, as an input for one of multiple selectable multiplexing operations. The multiplexing circuit further includes a selection signal input, coupled to the EX-OR element, the multiplexer element and the summer element, for receiving a selection signal that enables one or more of the EX-OR element, the multiplexer element, and the summer element. Non-enabled elements are powered down to eliminate jitter and performance penalties.

摘要翻译： 适用于锁相环应用的可配置复用电路和布置。 复用电路包括EX-OR元件，复用器元件和加法元件。 每个元件被配置为接收特定类型的检测信号输出，作为多个可选复用操作之一的输入。 复用电路还包括耦合到EX-OR元件的选择信号输入，多路复用器元件和加法元件，用于接收使EX-OR元件，多路复用器元件和夏天中的一个或多个的选择信号 元件。 未使能的元件掉电，以消除抖动和性能损失。

公开(公告)号：US6122203A

公开(公告)日：2000-09-19

申请号：US107000

申请日：1998-06-29

申请人： Jeffery Scott Hunt ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna ,  Jeffrey W. Waldrip ,  Satish C. Saripella

发明人： Jeffery Scott Hunt ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna ,  Jeffrey W. Waldrip ,  Satish C. Saripella

IPC分类号： G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22

摘要： A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.

摘要翻译： 一种包括存储器，第一锁存器，第二锁存器和控制电路的电路和方法。 存储器可以被配置为响应于（i）输入数据信号和（ii）地址信号来写入信息。 第一锁存器可以被配置为响应于控制信号保持地址。 第二锁存器可以被配置为响应于控制信号保持数据输入信号。 控制电路可以被配置为响应于（i）使能信号和（ii）检测信号来呈现控制信号。