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    Salicide process and method of fabricating semiconductor device using the same
    2.
    发明申请
    Salicide process and method of fabricating semiconductor device using the same 有权
    硅化物工艺及其制造使用其的半导体器件的方法

    公开(公告)号：US20060063380A1

    公开(公告)日：2006-03-23

    申请号：US11199439

    申请日：2005-08-08

    申请人： Sug-Woo Jung ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Kwan-Jong Roh ,  Eun-Ji Jung ,  Hyun-Su Kim

    发明人： Sug-Woo Jung ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Kwan-Jong Roh ,  Eun-Ji Jung ,  Hyun-Su Kim

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.

    摘要翻译： 形成金属硅化物层的方法包括将金属层转化为金属硅化物层的基于对流的退火步骤。 这些方法可以包括在衬底上形成硅层并形成与硅层直接接触的金属层（例如，镍层）。 然后执行步骤以将至少一部分金属层转化为金属硅化物层。 该转化步骤包括在对流或传导装置中将金属层暴露于惰性传热气体（例如氩气，氮气）。

    Methods of forming semiconductor devices having stacked transistors
    5.
    发明授权
    Methods of forming semiconductor devices having stacked transistors 失效
    形成具有层叠晶体管的半导体器件的方法

    公开(公告)号：US07435634B2

    公开(公告)日：2008-10-14

    申请号：US11398192

    申请日：2006-04-05

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/84

    CPC分类号： H01L21/8221 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76898 ,  H01L27/0688 ,  Y10S257/903

    摘要： A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成层间绝缘层，并且层间绝缘层可以具有暴露半导体衬底的一部分的接触孔。 可以在接触孔中和在与半导体衬底相对的接触孔附近的层间绝缘层的部分上形成单晶半导体插塞，并且与半导体衬底相对的部分层间绝缘层可以不含单晶半导体插头。 可以去除接触孔中的单晶半导体插塞的部分，同时将单晶半导体插塞的部分保持在与接触孔相邻的层间绝缘层的部分上作为单晶半导体接触图案。 在去除单晶半导体插头的部分之后，可以在层间绝缘层和单晶半导体接触图案上形成单晶半导体层。 可以在单晶半导体层上形成第二层间绝缘层，并且可以通过单晶半导体层通过第二层间绝缘层形成公共接触孔，并且通过第一层间绝缘层暴露半导体的一部分 基质。 此外，可以在与半导体衬底接触的公共接触孔中形成导电接触插塞。 还讨论了相关设备。

    Stacked semiconductor device and method of fabrication
    6.
    发明申请
    Stacked semiconductor device and method of fabrication 有权
    叠层半导体器件及其制造方法

    公开(公告)号：US20060197117A1

    公开(公告)日：2006-09-07

    申请号：US11368418

    申请日：2006-03-07

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L29/768

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

    摘要翻译： 叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜 形成在上层晶体管上的较低层间绝缘膜上。 叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层 以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
    7.
    发明申请
    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 有权
    堆叠半导体器件和制造方法

    公开(公告)号：US20080199991A1

    公开(公告)日：2008-08-21

    申请号：US12108591

    申请日：2008-04-24

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/84

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

    摘要翻译： 叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜 形成在上层晶体管上的较低层间绝缘膜上。 叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层 以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

    Stacked semiconductor device and method of fabrication
    8.
    发明授权
    Stacked semiconductor device and method of fabrication 有权
    叠层半导体器件及其制造方法

    公开(公告)号：US07687331B2

    公开(公告)日：2010-03-30

    申请号：US12108591

    申请日：2008-04-24

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/84

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

    摘要翻译： 叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜 形成在上层晶体管上的较低层间绝缘膜上。 叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层 以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

    Method of forming MOS transistor having fully silicided metal gate electrode
    10.
    发明申请
    Method of forming MOS transistor having fully silicided metal gate electrode 审中-公开
    形成具有完全硅化金属栅电极的MOS晶体管的方法

    公开(公告)号：US20060199343A1

    公开(公告)日：2006-09-07

    申请号：US11346607

    申请日：2006-02-01

    申请人： Sug-Woo Jung ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Hyun-Su Kim ,  Eun-Ji Jung

    发明人： Sug-Woo Jung ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Hyun-Su Kim ,  Eun-Ji Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7834 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

    摘要： A method of fabricating a MOS transistor having a fully silicided metal gate electrode is provided. The method includes forming a gate sacrificial pattern and protrusion regions on the gate pattern and active regions of a semiconductor substrate. The gate sacrificial pattern and the protrusion regions then undergo a silicidation process. A reduced gate pattern is formed by disposing an interlayer-insulating layer on semiconductor substrate having the silicided gate sacrificial pattern and silicided protrusion regions, and planarizing the interlayer-insulating layer. The fully silicided metal gate electrode is then formed by siliciding the reduced gate pattern.

    摘要翻译： 提供一种制造具有完全硅化金属栅电极的MOS晶体管的方法。 该方法包括在半导体衬底的栅极图案和有源区上形成栅极牺牲图案和突起区域。 然后，栅极牺牲图案和突起区域经历硅化处理。 通过在具有硅化栅牺牲图案和硅化突起区域的半导体衬底上设置层间绝缘层，并平坦化层间绝缘层，形成缩小的栅极图案。 然后通过将减小的栅极图案硅化来形成完全硅化金属栅电极。