公开(公告)号：US08884440B2

公开(公告)日：2014-11-11

申请号：US13603978

申请日：2012-09-05

申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-lyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-lyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

公开(公告)号：US08697583B2

公开(公告)日：2014-04-15

申请号：US13224737

申请日：2011-09-02

申请人： Kyung-seok Oh ,  Kyung-mun Byun ,  Shin-hye Kim ,  Deok-young Jung ,  Gil-heyun Choi ,  Eunkee Hong

发明人： Kyung-seok Oh ,  Kyung-mun Byun ,  Shin-hye Kim ,  Deok-young Jung ,  Gil-heyun Choi ,  Eunkee Hong

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/76224

摘要： Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.

摘要翻译： 根据本发明的实施方案提供的是氧化促进组合物，形成氧化物层的方法和制造半导体器件的方法。 在本发明的一些实施方案中，氧化促进组合物包括具有AML结构的氧化促进剂，其中L是化学吸附在硅表面，氧化硅，氮化硅或金属上的官能团，A是 一种可热分解的氧化官能团，M是允许A和L彼此共价结合的部分。

公开(公告)号：US20140021633A1

公开(公告)日：2014-01-23

申请号：US13919580

申请日：2013-06-17

申请人： Do-Sun Lee ,  Kun-Sang Park ,  Byung-Lyul Park ,  Seong-min Son ,  Gil-heyun Choi

发明人： Do-Sun Lee ,  Kun-Sang Park ,  Byung-Lyul Park ,  Seong-min Son ,  Gil-heyun Choi

IPC分类号： H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/2885 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

摘要： An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.

摘要翻译： 提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件及其制造方法。 集成电路器件可以包括穿透半导体结构的TSV结构。 TSV结构可以包括包括第一浓度的杂质的第一通过电极单元和包括大于第一浓度的第二浓度的杂质的第二通过电极单元。

公开(公告)号：US08546256B2

公开(公告)日：2013-10-01

申请号：US13167225

申请日：2011-06-23

申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

IPC分类号： H01L21/283

CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

公开(公告)号：US08546162B2

公开(公告)日：2013-10-01

申请号：US13243763

申请日：2011-09-23

申请人： Dae-Lok Bae ,  Byung-Lyul Park ,  Pil-Kyu Kang ,  Gil-Heyun Choi ,  Kwang-Jin Moon

发明人： Dae-Lok Bae ,  Byung-Lyul Park ,  Pil-Kyu Kang ,  Gil-Heyun Choi ,  Kwang-Jin Moon

IPC分类号： H01L21/00

CPC分类号： G02B6/138 ,  G02B6/136

摘要： A method for forming a light guide layer with improved transmission reliability in a semiconductor substrate, the method including forming a trench in the semiconductor substrate, forming a cladding layer and a preliminary light guide layer in the trench such that only one of opposite side end portions of the preliminary light guide layer is in contact with an inner sidewall of the trench, and performing a thermal treatment on the substrate to change the preliminary light guide layer into the light guide layer.

摘要翻译： 一种在半导体衬底中形成具有改善的透射可靠性的导光层的方法，所述方法包括在所述半导体衬底中形成沟槽，在所述沟槽中形成包覆层和预备导光层，使得只有一个相对侧端部 所述预备光导层与所述沟槽的内侧壁接触，并对所述基板进行热处理，以将所述初步导光层改变为所述导光层。

公开(公告)号：US08486783B2

公开(公告)日：2013-07-16

申请号：US12658520

申请日：2010-02-11

申请人： Woong-hee Sohn ,  Byung-hee Kim ,  Dae-yong Kim ,  Min-sang Song ,  Gil-heyun Choi ,  Kwang-jin Moon ,  Hyun-su Kim ,  Jang-hee Lee ,  Eun-ji Jung ,  Eun-ok Lee

发明人： Woong-hee Sohn ,  Byung-hee Kim ,  Dae-yong Kim ,  Min-sang Song ,  Gil-heyun Choi ,  Kwang-jin Moon ,  Hyun-su Kim ,  Jang-hee Lee ,  Eun-ji Jung ,  Eun-ok Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/456 ,  H01L29/66666

摘要： A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

摘要翻译： 一种制造半导体器件的方法包括：通过蚀刻衬底形成用于形成掩埋型线的沟槽; 在沟槽的底部和沟槽的壁上分别形成第一和第二氧化层; 去除一部分第一氧化层和整个第二氧化层; 以及通过在去除所述第二氧化层的所述沟槽的壁上执行硅化物处理，在所述沟槽的壁上形成所述埋入式导线。 结果，埋入式电线彼此绝缘。

公开(公告)号：US08404579B2

公开(公告)日：2013-03-26

申请号：US12960150

申请日：2010-12-03

申请人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

发明人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC分类号： H01L21/44

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

摘要翻译： 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US20130062719A1

公开(公告)日：2013-03-14

申请号：US13614730

申请日：2012-09-13

申请人： Pil-Kyu KANG ,  Joong-Han SHIN ,  Byung-Lyul PARK ,  Gil-Heyun CHOI

发明人： Pil-Kyu KANG ,  Joong-Han SHIN ,  Byung-Lyul PARK ,  Gil-Heyun CHOI

IPC分类号： H01L31/0232

CPC分类号： G02B6/4206 ,  G02B6/12004 ,  G02B6/42 ,  G02B6/4201 ,  G02B6/4204 ,  H01L31/0232

摘要： An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.

摘要翻译： 提供光输入/输出（I / O）设备。 该装置包括：包括上沟槽的衬底; 布置在所述衬底的上沟槽内的波导; 光电检测器，设置在所述衬底的上沟槽内，并且包括光学连接到所述波导的端面的第一端面; 以及插入在波导的端面与光检测器的第一端面之间的透光绝缘层。

公开(公告)号：US20120314991A1

公开(公告)日：2012-12-13

申请号：US13412210

申请日：2012-03-05

申请人： Pil-Kyu Kang ,  Dae-Lok Bae ,  Byung-Lyul Park ,  Gil-Heyun Choi

发明人： Pil-Kyu Kang ,  Dae-Lok Bae ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC分类号： G02B6/12 ,  H01L29/06

CPC分类号： G02B6/124 ,  G02B6/136 ,  G02B6/4206 ,  G02B6/43

摘要： Semiconductor devices having an optical transceiver include a cladding on a substrate, a protrusion vertically extending trough the cladding and materially in continuity with the substrate, and a coupler on the cladding and the protrusion.

摘要翻译： 具有光收发器的半导体器件包括在衬底上的包层，垂直延伸穿过覆层并与衬底物理连续的突起，以及在包层和突起上的耦合器。

公开(公告)号：US08304343B2

公开(公告)日：2012-11-06

申请号：US13240109

申请日：2011-09-22

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。